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1.8 volt intel ? wireless flash memory (w18) 28F320W18, 28f640w18, 28f128w18 preliminary datasheet product features the 1.8 volt intel ? wireless flash memory with flexible multi-partition dual-operation provides high- performance asynchronous and synchronous burst reads. it is an ideal memory for low-voltage burst cpus. combining high read performance with flash memory ? s intrinsic non-volatility, 1.8 volt intel wireless flash memory eliminates the traditional system-performance paradigm of shadowing redundant code memory from slow nonvolatile storage to faster execution memory. it reduces the total memory requirement that increases reliability and reduces overall system power consumption and cost. the 1.8 volt intel wireless flash memory ? s flexible multi-partition architecture allows programming or erasing to occur in one partition while reading from another partition. this allows for higher data write throughput compared to single partition architectures. the dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. the designer can also choose the size of the code and data partitions via the flexible multi-partition architecture. the 1.8 volt intel wireless flash memory is manufactured on intel ? s 0.18 m etox ? vii process technology. it is available in bga and vf bga packages which are ideal for board-constrained applications. performance ? 70 ns asynchronous reads for 32 and 64 mbit, 90 ns for 128 mbit ? 14 ns clock to data output (t chqv ) ? 20 ns page mode read speed ? 4-word, 8-word, and continuous-word burst modes ? burst and page modes in parameter and main partitions ? programmable wait configuration ? enhanced factory programming mode@ 3.50 s/word (typ) ? glueless 12 v interface for fast factory programming @ 8 s/word (typ) ? 1.8 v low-power programming @ 12 s/word (typ) ? program or erase during reads architecture ? multiple 4-mbit partitions ? dual-operation: read-while-write or read- while-erase ? eight, 4-kword parameter code and data blocks ? 32-kword main code and data blocks ? top and bottom parameter configurations power operation ? 1.7 v to 1.95 v read and write operations ? 1.7 v to 2.24 v v ccq for i/o isolation ? standby current: 5 a (typ) ? read current: 7 ma (typ) software ? 5 s (typ) program suspend ? 5 s (typ) erase suspend ? intel ? flash data integrator (fdi) software optimized ? intel basic command set compatible ? common flash interface (cfi) quality and reliability ? extended temperature: ? 40 c to +85 c ? minimum 100,000 erase cycles per block ? etox ? vii flash technology (0.18 m) security ? 128-bit protection register: 64 unique device identifier bits; 64 user-programmable otp bits ? absolute write protection ? v pp = gnd ? erase/program lockout during power transitions ? individual dynamic zero-latency block locking ? individual block lock-down density and packaging ? 32 mbit and 128 mbit in a vf bga package ? 64 mbit in a bga*package ? 56 active ball matrix, 0.75 mm ball-pitch bga* and vf bga packages ? 16-bit wide data bus 290701-003 june 2001 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such p roducts, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includ ing liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual p roperty right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 1.8 volt intel? wireless flash memory may contain design defects or errors known as errata which may cause the product to d eviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2001. *other names and brands may be claimed as the property of others.
iii 1.8 volt intel? wireless flash memory (w18) contents 1.0 introduction .................................................................................................................. 1 1.1 document conventions ......................................................................................... 1 1.2 product overview .................................................................................................. 2 2.0 product description .................................................................................................. 4 2.1 package and ballouts............................................................................................ 4 2.2 signal descriptions................................................................................................ 4 2.3 memory partitioning .............................................................................................. 6 3.0 principles of operation ............................................................................................ 9 3.1 bus operations...................................................................................................... 9 3.1.1 read......................................................................................................... 9 3.1.2 standby ..................................................................................................10 3.1.3 write .......................................................................................................10 3.1.4 reset ......................................................................................................10 4.0 command definitions .............................................................................................11 4.1 read-while-write and read-while-erase...........................................................11 4.2 read array command.........................................................................................14 4.3 read identifier command ...................................................................................14 4.4 read query command .......................................................................................15 4.5 read status register command.........................................................................15 4.6 clear status register command.........................................................................17 4.7 word program command ...................................................................................17 4.8 block erase command........................................................................................18 4.9 program suspend, program resume, erase suspend, erase resume commands .................................................................................20 4.10 enhanced factory program command (efp) ....................................................23 4.10.1 efp requirements and considerations .................................................23 4.10.2 setup phase...........................................................................................24 4.10.3 program phase ......................................................................................24 4.10.4 verify phase ...........................................................................................24 4.10.5 exit phase ..............................................................................................25 4.11 security modes....................................................................................................27 4.12 block locking commands...................................................................................27 4.12.1 lock block ..............................................................................................28 4.12.2 unlock block...........................................................................................28 4.12.3 lock-down block....................................................................................28 4.12.4 block lock status...................................................................................29 4.12.5 locking operations during erase suspend ...........................................29 4.12.6 status register error checking..............................................................29 4.12.7 wp# lock-down control ........................................................................30 4.13 protection register..............................................................................................30 4.14 read protection register ....................................................................................31 4.15 program protection register ...............................................................................31 4.15.1 lock protection register ........................................................................32 4.16 set configuration register ..................................................................................34
1.8 volt intel ? wireless flash memory ( w18) iv 4.16.1 read mode (cr.15) ............................................................................... 35 4.16.2 first access latency count (cr.13-11)................................................. 35 4.16.3 wait signal polarity (cr.10)................................................................. 37 4.16.4 wait signal function ............................................................................ 38 4.16.5 data output configuration (cr.9) .......................................................... 38 4.16.6 wait delay configuration (cr.8) .......................................................... 39 4.16.7 burst sequence configuration (cr.7).................................................... 40 4.16.8 clock configuration (cr.6) .................................................................... 41 4.16.9 burst wrap (cr.5).................................................................................. 41 4.16.10 burst length (cr.2-0) ............................................................................ 42 5.0 program and erase voltages .............................................................................. 43 5.1 factory program mode ....................................................................................... 43 5.2 programming voltage protection (vpp).............................................................. 43 6.0 power consumption ............................................................................................... 44 6.1 active power ....................................................................................................... 44 6.2 automatic power savings ................................................................................... 44 6.3 standby power.................................................................................................... 44 6.4 power-up/down operation ................................................................................. 44 6.4.1 system reset and rst#........................................................................ 44 6.4.2 vcc, vpp, and rst# transitions.......................................................... 45 6.4.3 power supply decoupling ...................................................................... 45 7.0 electrical specifications ........................................................................................ 46 7.1 absolute maximum ratings ................................................................................ 46 7.2 extended temperature operation....................................................................... 47 7.3 capacitance ........................................................................................................ 47 7.4 dc characteristics .............................................................................................. 48 7.5 ac i/o test conditions ....................................................................................... 50 7.6 ac read characteristics..................................................................................... 51 7.7 ac write characteristics ..................................................................................... 61 7.8 erase and program times .................................................................................. 63 7.9 reset specifications............................................................................................ 63 appendix a write state machine states ............................................................................. 65 appendix b common flash interface ................................................................................. 68 appendix c mechanical specifications .............................................................................. 76 appendix d ordering information ......................................................................................... 77
v 1.8 volt intel ? wireless flash memory (w18) revision history date of revision version description 09/13/00 290701-001 original version 01/29/01 290701-002 deleted 16-mbit density revised adv#, section 2.2 revised protection registers , section 4.16 revised program protection register , section 4.18 revised example in first access latency count , section 5.0.2 revised figure 5, data output with lc setting at code 3 added wait signal function , section 5.0.3 revised wait signal polarity , section 5.0.4 revised data output configuration , section 5.0.5 added figure 7, data output configuration with wait signal delay revised wait delay configuration , section 5.0.6 changed v ccq spec from 1.7 v ? 1.95 v to 1.7 v ? 2.24 v in section 8.2, extended temperature operation changed i ccs spec from 15 a to 18 a in section 8.4, dc characteristics changed i ccr spec from 10 ma (clk = 40 mhz, burst length = 4) and 13 ma (clk = 52 mhz, burst length = 4) to 13 ma, and 16 ma respectively in section 8.4, dc characteristics changed i ccws spec from 15 a to 18 a in section 8.4, dc characteristics changed i cces spec from 15 a to 18 a in section 8.4, dc characteristics changed t chqx spec from 5ns to 3ns in section 8.6, ac read characteristics added figure 25, wait signal in synchronous non-read array operation waveform added figure 26, wait signal in asynchronous page mode read operation waveform added figure 27, wait signal in asynchronous single word read operation waveform revised appendix e, ordering information 06/12/01 290701-003 revised entire section 4.10, enhanced factory program command (efp) and figure 6, enhanced factory program flowchart revised section 4.13, protection register revised section 4.15, program protection register revised section 7.3, capacitance, to include 128-mbit specs revised section 7.4, dc characteristics, to include 128-mbit specs revised section 7.6, ac read characteristics, to include 128-mbit device specifications added t vhgl spec in section 7.6, ac read characteristics revised section 7.7, ac write characteristics , to include 128-mbit device specifications minor text edits

1.8 volt intel ? wireless flash memory (w18) preliminary 1 1.0 introduction this datasheet contains information about the 1.8 volt intel ? wireless flash memory family. section 1.0 provides a flash memory overview. section 2.0 through section 6.0 describe the memory functionality. section 7.0 describes the electrical specifications for extended temperature product offerings. 1.1 document conventions many terms and phrases are used throughout this document as a short-hand version of full, and more accurate verbiage: the term ? 1.8 v ? refers to the full vcc voltage range of 1.7 v ? 1.95 v (except where noted) and ? v pp =12v ? refers to 12 v 5%. when referring to registers, the term set means the bit is a ? 1 ? , and clear means the bit is a ? 0 ? . even though this product supports multiple package types, the terms pin and signal are often used interchangeably to refer to the external signal connections on the package. (e.g., balls in the case of bga*). a word is 2 bytes, or 16 bits. for voltage and ground signals, the signal name is denoted in all caps as seen in section 2.2, ? signal descriptions ? on page 4 , whereas the voltage applied to the signal uses subscripted notation. for example vpp refers to a signal, while v pp is a voltage level. throughout this document, references are made to top, bottom, parameter, and main partitions. to clarify these references, the following conventions have been adopted: a block is a group of bits (or words) that erase simultaneously with one block erase instruction. a main block contains 32 kwords. a parameter block contains 4 kwords. the block base address (bba) is the first address of a block. a partition is a group of blocks that share erase and program circuitry and a common status register. if one block is erasing or one word is programming, only the status register, rather than array data, is available when any address within the same partition is read. the partition base address (pba) is the first address of a partition. for example, on a 32- mbit top-parameter device, partition number 5 has a pba of 140000h. the top partition is located at the highest physical device address. this partition may be a main partition or a parameter partition. the bottom partition is located at the lowest physical device address. this partition may be a main partition or a parameter partition. a main partition contains only main blocks. a parameter partition contains a mixture of main and parameter blocks. a top parameter device ( tpd ) has the parameter partition at the top of the memory map with the parameter blocks at the top of that partition. this was formerly referred to as top-boot device.
1.8 volt intel ? wireless flash memory (w18) 2 preliminary a bottom parameter device ( bpd ) has the parameter partition at the bottom of the memory map with the parameter blocks at the bottom of that partition. this was formerly referred to as bottom-boot block flash device. additionally, many acronyms which describe product features or usage are used throughout the document. they are defined here: efp : enhanced factory programming rww : read-while-write rwe : read-while-erase cfi : common flash interface cui : command user interface wsm : write state machine otp : one-time programmable pba : partition base address bba : block base address aps : automatic power savings fdi : flash data integrator srd : status register data 1.2 product overview the 1.8 volt intel ? wireless flash memory provides rww/rwe capability with high- performance synchronous and asynchronous reads on package-compatible densities with a 16-bit data bus. individually-erasable memory blocks are optimally sized for code and data storage. eight 4-kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. the rest of the memory array is grouped into 32-kword main blocks. the memory architecture for the 1.8 v intel wireless flash memory consists of multiple 4-mbit partitions, the exact number depending on device density. by dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. burst reads can traverse partition boundaries, but user application code is responsible for ensuring that they don ? t extend into a partition that is actively programming or erasing. although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. augmented erase suspend functionality further enhances the rww capabilities of this device. an erase can be suspended to perform a program or read operation within any block, except that which is erase-suspended. a program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. after device power-up or reset, the 1.8 volt intel wireless flash memory defaults to asynchronous read configuration. writing to the device ? s configuration register enables synchronous burst-mode read operation. in synchronous mode, the clk input increments an internal burst address generator. clk also synchronizes the flash memory with the host cpu and outputs data on every, or on every other, clk cycle after initial latency. a programmable wait output signal provides easy cpu-to-flash memory synchronization.
1.8 volt intel ? wireless flash memory (w18) preliminary 3 in addition to its enhanced architecture and interface, the 1.8 volt intel wireless flash memory incorporates technology that enables fast factory programming and low-power designs. the efp option renders the fastest available program performance, which can increase a factory ? s manufacturing throughput. the device supports read operations at 1.8 v v cc and erase and program operations at 1.8 v or 12 v v pp . with the 1.8 v v pp option, vcc and vpp can be tied together for a simple, ultra-low- power design. in addition to voltage flexibility, the dedicated vpp input provides complete data protection when v pp v pplk . a 128-bit protection register enhances the user ? s ability to implement new security techniques and data protection schemes. unique flash device identification and fraud-, cloning-, or content- protection schemes are possible via a combination of intel-programmed and user-otp data cells. zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. an additional block lock-down capability provides hardware protection where software commands alone cannot change the block ? s protection status. the device ? s cui is the system processor ? s link to internal flash memory operation. a valid command sequence written to the cui initiates device wsm operation that automatically executes the algorithms, timings, and verifications necessary to manage flash memory program and erase. an internal status register provides ready/busy indication results of the operation (success, fail, etc.). three power-savings features, aps, standby, and rst#, can significantly reduce power consumption. the device automatically enters aps mode following read cycle completion. standby mode begins when the system deselects the flash memory by deasserting ce#. driving rst# low produces power savings similar to standby mode. it also resets the part to read array mode (important for system-level reset), clears internal status registers, and provides an additional level of flash write protection.
1.8 volt intel ? wireless flash memory (w18) 4 preliminary 2.0 product description 2.1 package and ballouts the 1.8 volt intel ? wireless flash memory is available in 56 active ball matrix bga* and vf bga chip scale packages with 0.75 mm ball pitch that is ideal for board-constrained applications. figure 1, ?56 active ball matrix bga* and vf bga packages? on page 4 shows device ballout. notes: 1. on lower density devices, upper address balls can be treated as nc. (example: for 32-mbit density, a[21] and a[22] will be nc). 2. see appendix c, ?mechanical specifications? on page 76 for package mechanical specifications. 2.2 signal descriptions table 1, ?signal descriptions? on page 5 describes ball usage. figure 1. 56 active ball matrix bga* and vf bga packages a b c d e f g a b c d e f g top view - ball side down complete ink mark not shown 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 bottom view - ball side up a4 a6 a18 vpp vcc vss a8 a11 a3 a5 a17 rst# clk a20 a9 a12 a2 a7 we# adv# a19 a10 a13 a1 a14 wp# dq12 a16 wait a15 a0 ce# dq1 dq2 dq4 dq6 dq15 vccq oe# dq0 dq9 dq10 dq11 dq13 dq14 vss vssq dq8 vccq dq3 vcc dq5 vssq dq7 a22 a21 a4 a6 a18 vpp vcc vss a8 a11 a3 a5 a17 rst# clk a20 a9 a12 a2 a7 we# adv# a19 a10 a13 a1 a14 wp# dq12 a16 wait a15 a0 ce# dq1 dq2 dq4 dq6 dq15 vccq oe# dq0 dq9 dq10 dq11 dq13 dq14 vss vssq dq8 vccq dq3 vcc dq5 vssq dq7 a22 a21
1.8 volt intel ? wireless flash memory (w18) preliminary 5 table 1. signal descriptions symbol type name and function a[22:0] i address inputs: for memory addresses. 32 mbit: a[20:0]; 64 mbit: a[21:0]; 128 mbit: a[22:0] dq[15:0] i/o data input/outputs: inputs data and commands during write cycles, outputs data during memory, status register, protection register, and configuration code reads. data pins float when the chip or outputs are deselected. data is internally latched during writes. adv# i address valid: adv# indicates valid address presence on address inputs. during synchronous read operations, all addresses are latched on adv# ? s rising edge or clk ? s rising (or falling) edge, whichever occurs first. ce# i chip enable: ce#-low activates internal control logic, i/o buffers, decoders, and sense amps. ce#- high deselects the device, places it in standby state, and places data and wait outputs at high-z. clk i clock: clk synchronizes the device to the system bus frequency in synchronous-read configuration and increments an internal burst address generator. during synchronous read operations, addresses are latched on adv# ? s rising edge or clk ? s rising (or falling) edge, whichever occurs first. oe# i output enable: active low oe# enables the device ? s output data buffers during a read cycle. with oe# at v ih , device data outputs are placed in high-z state. rst# i reset: when low, rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst#-high enables normal operation. exit from reset places the device in asynchronous read array mode. wait o wait: indicates data valid in synchronous read modes. configuration register bit 10 (cr.10, wt) determines its polarity when set to ? 1 ? . with ce# at v il , wait ? s active output is v ol or v oh . wait is high-z if ce# is v ih . wait is not gated by oe#. we# i write enable: we# controls writes to the cui and array. addresses and data are latched on the we# pulse ? s rising edge. wp# i write protect: disables/enables the lock-down function. when wp# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. see section 4.12, ? block locking commands ? on page 27 for details on block locking. vpp pwr/i erase and program power: a valid v pp voltage on this pin allows erase or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, v pp ? s v ih level can be as low as v pp1 min. v pp must remain above v pp1 min to perform in-system flash modification. vpp may be 0 v during read operations. v pp2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 12 v for a cumulative total not to exceed 80 hours maximum. extended use of this pin at 12 v may reduce block cycling capability. vcc pwr device power supply: writes are inhibited at v cc v lko . device operations at invalid v cc voltages should not be attempted. vccq pwr output power supply: enables all outputs to be driven at v ccq . this input may be tied directly to vcc. vss pwr ground: pins for all internal device circuitry must be connected to system ground. vssq pwr output ground : provides ground to all outputs which are driven by vccq. this signal may be tied directly to vss. du don ? t use: do not use this pin. this pin should not be connected to any power supplies, signals or other pins and must be floated. nc no connect: no internal connection; can be driven or floated.
1.8 volt intel ? wireless flash memory (w18) 6 preliminary 2.3 memory partitioning the 1.8 volt intel ? wireless flash memory is divided into 4-mbit physical partitions which allows simultaneous rww or rwe operations and allows users to segment code and data areas on 4-mbit boundaries. the device ? s asymmetrically-blocked architecture enables system code and data integration within a single flash device. each block can be erased independently in block erase mode. simultaneous program and erase is not allowed. only one partition at a time can be actively programming or erasing. see table 2, ? bottom parameter memory map ? on page 7 and table 3, ? top parameter memory map ? on page 8 . the 32-mbit device has eight partitions, the 64-mbit device has 16 partitions, and the 128-mbit device has 32 partitions. each device density contains one parameter partition and several main partitions: the 4-mbit parameter partition contains eight 4-kword parameter blocks and seven 32- kword main blocks; and each 4-mbit main partition contains eight 32-kword blocks each. the bulk of the array is divided into main blocks that can store code or data, and parameter blocks allow storage of frequently updated small parameters that would normally be stored in eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. . .
1.8 volt intel ? wireless flash memory (w18) preliminary 7 table 2. bottom parameter memory map size (kw) blk # 32 mbit blk # 64 mbit blk # 128 mbit main partitions sixteen partitions 32 262 7f8000-7fffff ... ... ... 32 135 400000-407fff eight partitions 32 134 3f8000-3fffff 134 3f8000-3fffff ... ... ... ... ... 32 71 200000-207fff 71 200000-207fff four partitions 32 70 1f8000-1fffff 70 1f8000-1fffff 70 1f8000-1fffff ... ... ... ... ... ... ... 32 39 100000-107fff 39 100000-107fff 39 100000-107fff one partition 32 38 0f8000-0fffff 38 0f8000-0fffff 38 0f8000-0fffff ... ... ... ... ... ... ... 32 31 0c0000-0c7fff 31 0c0000-0c7fff 31 0c0000-0c7fff one partition 32 30 0b8000-0bffff 30 0b8000-0bffff 30 0b8000-0bffff ... ... ... ... ... ... ... 32 23 080000-087fff 23 080000-087fff 23 080000-087fff one partition 32 22 078000-07ffff 22 078000-07ffff 22 078000-07ffff ... ... ... ... ... ... ... 32 15 040000-047fff 15 040000-047fff 15 040000-047fff parameter partition one partition 32 14 038000-03ffff 14 038000-03ffff 14 038000-03ffff ... ... ... ... ... ... ... 32 8 008000-00ffff 8 008000-00ffff 8 008000-00ffff 4 7 007000-007fff 7 007000-007fff 7 007000-007fff ... ... ... ... ... ... ... 4 0 000000-000fff 0 000000-000fff 0 000000-000fff
1.8 volt intel ? wireless flash memory (w18) 8 preliminary 3.0 principles of operation the 1.8 volt intel ? wireless flash memory family includes an on-chip wsm to manage block erase and program algorithms. its cui allows minimal processor overhead with ram-like interface timings. table 3. top parameter memory map size (kw) blk # 32 mbit blk # 64 mbit blk # 128 mbit parameter partition one partition 4 70 1ff000-1fffff 134 3ff000-3fffff 262 7ff000-7fffff ... ... ... ... ... ... ... 4 63 1f8000-1f8fff 127 3f8000-3f8fff 255 7f8000-7f8fff 32 62 1f0000-1f7fff 126 3f0000-3f7fff 254 7f0000-7f7fff ... ... ... ... ... ... ... 32 56 1c0000-1c7fff 120 3c0000-3c7fff 248 7c0000-7c7fff main partitions one partition 32 55 1b8000-1bffff 119 3b8000-3bffff 247 7b8000-7bffff ... ... ... ... ... ... ... 32 48 18000-187fff 112 380000-387fff 240 780000-787fff one partition 32 47 178000-17ffff 111 378000-37ffff 239 778000-77ffff ... ... ... ... ... ... ... 32 40 140000-147fff 104 340000-347fff 232 740000-747fff one partition 32 39 138000-13ffff 103 338000-33ffff 231 738000-73ffff ... ... ... ... ... ... ... 32 32 100000-107fff 96 300000-307fff 224 700000-707fff four partitions 32 31 0f8000-0fffff 95 2f8000-2fffff 223 6f8000-6fffff ... ... ... ... ... ... ... 32 0 000000-007fff 64 200000-207fff 192 600000-607fff eight partitions 32 63 1f8000-1fffff 191 5f8000-5fffff ... ... ... ... ... 32 0 000000-007fff 128 400000-407fff sixteen partitions 32 127 3f8000-3fffff ... ... ... 32 0 000000-007fff
1.8 volt intel ? wireless flash memory (w18) preliminary 9 3.1 bus operations notes: 1. manufacturer and device codes are accessed in read identifier mode (a[max:1]=0). 2. query accesses use only dq[7:0]. all other accesses use dq[15:0]. 3. x must be v il or v ih for control pins and addresses. 4. rst# must be at v ss 0.2 v to meet the maximum specified power-down current. 5. refer to the table 6, ?bus cycle definitions? on page 13 for valid d in during a write operation. 3.1.1 read the 1.8 volt intel wireless flash memory has several read configurations: asynchronous page mode read. synchronous burst mode read. ? outputs four, eight, or continuous words, from main blocks and parameter blocks. the device ? s partitions have several available read modes: read array mode: read accesses return flash array data from the addressed locations. read identifier mode: reads return manufacturer and device identifier data, block lock status, and protection register data. the identification plane occupies the 4-mbit partition address locations corresponding to the command ? s address; the flash array is not accessible in read identifier mode. read query mode: reads return device cfi data. the query plane occupies the 4-mbit partition address locations corresponding to the command ? s address; the flash array is not accessible in read query mode. read status register mode: reads return status register data from the addressed partition. that partition ? s array data is not accessible. a system processor can check the status register to determine an addressed partition ? s state or monitor program and erase progress. all partitions support synchronous burst mode that internally sequences addresses with respect to the input clk to select and supply data to the outputs. identifier codes, query data, and status register read operations execute as single-synchronous or asynchronous read cycles. wait is inactive during these reads. access to the modes listed above is independent of v pp . an appropriate cui command places the device in a read mode. at initial power-up or after reset, the device defaults to asynchronous read array mode. table 4. bus operations mode note rst# ce# oe# we# adv# wait dq[15:0] read (array, status, configuration, identifier, or query) 1,2 v ih v il v il v ih v il valid only in synchronous mode d out output disable 3 v ih v il v ih v ih x high-z high-z standby 3 v ih v ih x x x high-z high-z reset 3,4 v il x x x x high-z high-z write 5 v ih v il v ih v il v il high-z d in
1.8 volt intel ? wireless flash memory (w18) 10 preliminary asserting ce# enables device read operations. the device internally decodes upper address inputs to determine which partition is accessed. adv#-active opens the internal address latches. asserting oe# activates the outputs and gates selected data onto the i/o bus. in asynchronous mode, the address is latched when adv# is deasserted (when the device is configured to use adv#). in synchronous mode, the address is latched by either the rising edge of adv# or the rising (or falling) clk edge while adv# remains asserted, whichever occurs first. we# and rst# must be at deasserted during read operations. 3.1.2 standby ce# inactive deselects the device and places it in standby mode, substantially reducing device power consumption. in standby mode, outputs are placed in a high-impedance state independent of oe#. if deselected during a program or erase algorithm, the device will consume active power until the program or erase operation completes. 3.1.3 write a write occurs when ce# and we# are asserted and oe# is deasserted. flash control commands are written to the cui using standard microprocessor write timings. the address and data are latched on the rising edge of we#. write operations are asynchronous; clk is ignored. the cui does not occupy an addressable memory location within any partition. the system processor must access it at the correct address range depending on the kind of command executed. programming or erasing may occur in only one partition at a time. other partitions must be in one of the read modes or erase suspend mode. table 5, ? command codes and descriptions ? on page 12 shows the available commands. appendix a, ? write state machine states ? on page 65 provides information on moving between different operating modes using cui commands. 3.1.4 reset the device enters a reset mode when rst# is driven low. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after returning from reset, a time t phqv is required until outputs are valid, and a delay (t phwv ) is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the device defaults to read array mode, the status register is set to 80h, and the configuration register defaults to asynchronous page-mode reads. if rst# is asserted during an erase or program operation, the operation will be aborted and the memory contents at the aborted block or address are invalid. see figure 29, ? reset operations waveforms ? on page 64 for detailed information regarding reset timings. like any automated device, it is important to assert rst# during system reset. when the system comes out of reset, the processor expects to read from the flash memory array. automated flash memories provide status information when read during program or erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. 1.8 volt intel ? flash memories allow proper cpu initialization following a system reset through the use of the rst# input. in this application, rst# is controlled by the same cpu reset signal, reset#.
1.8 volt intel ? wireless flash memory (w18) preliminary 11 4.0 command definitions the device ? s on-chip wsm manages erase and program algorithms. the local cpu controls the device ? s in-system read, program, and erase operations. bus cycles to or from the flash memory conform to standard microprocessor bus cycles. rst#, ce#, oe#, we#, and adv# control signals dictate data flow into and out of the device. wait informs the cpu of valid data during burst reads. table 4, ? bus operations ? on page 9 summarizes bus operations. device operations are selected by writing specific commands into the device ? s cui. table 5, ? command codes and descriptions ? on page 12 lists all possible command codes and descriptions, table 6, ? bus cycle definitions ? on page 13 lists command definitions. since commands are partition-specific, it is important to issue write commands within the target address range. multi-cycle command writes to a flash memory partition must be issued sequentially without intervening command writes. for example, an erase setup command to partition x must be immediately followed by the erase confirm command in order to be executed properly. the address given during the erase confirm command determines the location of the erase. if the erase confirm command is given to partition x, then the command will be executed and a block in partition x will be erased. alternatively, if the erase confirm command is given to partition y, the command will still be executed and a block in partition y will be erased. any other command given to any partition prior to the erase confirm command will result in a command sequence error, which is posted in the status register. after the erase is successfully started in partition x or y, read cycles may occur in any other partition z (e.g., code or data reads). 4.1 read-while-write and read-while-erase the 1.8 volt intel ? wireless flash memory supports flexible multi-partition dual-operation architecture. by dividing the flash memory into many separate partitions, the device is capable of reading from one partition while programing or erasing in another partition; hence the terms, rww and rwe. both of these features greatly enhance data storage performance. the product does not support simultaneous program and erase operations. attempting to perform operations such as these will result in a command sequence error. only one partition may be programming or erasing while another partition is reading. however, one partition may be in erase suspend mode while a second partition is performing a program operation, and yet another partition may be executing a read array command. table 5. command codes and descriptions mode code device command description read ffh read array places selected partition in read array mode. 70h read status register places selected partition in status register read mode. the partition enters this mode after a program or erase command is issued to it. 90h read identifier puts the selected partition in read identifier mode. device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, or protection register data on dq[15:0]. 98h read query puts the addressed partition in read query mode. device reads from the partition addresses output cfi information on dq[7:0]. 50h clear status register the wsm can set the status register ? s block lock (sr.1), v pp (sr.3), program (sr.4), and erase (sr.5) status bits, but it cannot clear them. sr.1,3,4,5 can only be cleared by a device reset or through the clear status register command.
1.8 volt intel ? wireless flash memory (w18) 12 preliminary note: do not use unassigned commands. intel reserves the right to redefine these codes for future functions. program 40h word program setup this preferred program command ? s first cycle prepares the cui for a program operation. the second cycle latches address and data and executes the wsm program algorithm at this location. status register updates occur when ce# or oe# is toggled. a read array command is required to read array data after programming. 10h alternate setup equivalent to a program setup command (40h). 30h efp setup this program command activates efp mode. the first write cycle sets up the command. if the second cycle is an efp confirm command (d0h), subsequent writes provide program data. all other commands are ignored once efp mode begins. d0h efp confirm if the first command was efp setup (30h), the cui latches the address and data and prepares the device for efp mode. erase 20h erase setup prepares the cui for block erase. the device erases the block addressed by the erase confirm command. if the next command is not erase confirm, the cui: (a) sets status register bits sr.4 and sr.5, (b) places the partition in the read status register mode, and (c) waits for another command. d0h erase confirm if the first command was erase setup (20h), the cui latches address and data and erases the block indicated by the erase confirm cycle address. during program or erase, the partition responds only to read status register, program suspend, and erase suspend commands. ce# or oe# toggle updates status register data. suspend b0h program suspend or erase suspend this command issued at any device address suspends the currently executing program or erase operation. the status register, invoked by a read status register command, indicates successful operation suspension by setting status bits sr.2 (program suspend) or sr.6 (erase suspend) and sr.7. the wsm remains in the suspend mode regardless of control signal states, except rst# = v il . d0h suspend resume this command issued at any device address resumes suspended program or erase operation. block locking 60h lock setup prepares the cui lock configuration. if the next command is not block-lock, unlock, or lock- down, the cui sets sr.4 and sr.5 to indicate command sequence error. 01h lock block if the previous command was lock setup (60h), the cui locks the addressed block. d0h unlock block if the previous command was lock setup (60h) command, the cui latches the address and unlocks the addressed block. if previously locked-down, the operation has no effect. 2fh lock-down if the previous command was lock setup (60h) command, the cui latches the address and locks-down the addressed block. protection c0h protection program setup prepares the cui for a protection register program operation. the second cycle latches address and data and starts the wsm ? s protection register program or lock algorithm. toggling ce# or oe# updates the flash status register data. to read array data after programming, issue a read array command. configuration 60h configuration setup prepares the cui for device configuration. if set configuration register is not the next command, the cui sets sr.4 and sr.5 to indicate command sequence error. 03h set configuration register if the previous command was configuration setup (60h), the cui latches the address and writes a[15:0] data into the configuration register. following a set configuration register command, subsequent read operations access array data. table 5. command codes and descriptions mode code device command description
1.8 volt intel ? wireless flash memory (w18) preliminary 13 notes: 1. first cycle command addresses should be the same as the operation ? s target address. examples: the first- cycle address for the read identifier command should be the same as the identification code address (ia); the first cycle address for the word program command should be the same as the word address (wa) to be programmed; the first cycle address for the erase/program suspend command should be the same as the address within the block to be suspended; etc. xx = any valid address within the device. ia = identification code address. ba = block address. any address within a specific block. lpa = lock protection address is obtained from the cfi (via the read query command). the 1.8 volt intel wireless flash memory family ? s lpa is at 0080h. pa = user programmable 4-word protection address in the device identification plane. pna = any address within a specific partition. pba = partition base address. the very first address of a particular partition. qa = query code address. wa = word address of memory location to be written. 2. srd = data read from the status register. wd = data to be written at location wa. ic = identifier code data. pd = user programmable 4-word protection data. qd = query code data on dq[7:0]. cd = configuration register code data presented on device addresses a[15:0]. a[max:16] address bits can select any partition . see table 12, ? configuration register definitions ? on page 34 for configuration register bits descriptions. 3. commands other than those shown above are reserved by intel for future device implementations and should not be used. table 6. bus cycle definitions mode command bus cycles first bus cycle second bus cycle oper addr (1) data (2,3) oper addr (1) data (2,3) read read array/reset 1 write pna ffh read identifier 2 write pna 90h read pba+ia ic read query 2 write pna 98h read pba+qa qd read status register 2 write pna 70h read ba srd clear status register 1 write xx 50h program erase block erase 2 write ba 20h write ba d0h word program 2 write wa 40h/10h write wa wd efp > 2 write wa 30h write wa d0h program/erase suspend 1 write xx b0h program/erase resume 1 write xx d0h lock lock block 2 write ba 60h write ba 01h unlock block 2 write ba 60h write ba d0h lock-down block 2 write ba 60h write ba 2fh protec- tion protection program 2 write pa c0h write pa pd lock protection program 2 write lpa c0h write lpa fffdh config- uration set configuration register 2 write cd 60h write cd 03h
1.8 volt intel ? wireless flash memory (w18) 14 preliminary 4.2 read array command the read array command places (or resets) the partition in read array mode. upon initial device power-up or after reset (rst# transitions from v il to v ih ), all partitions default to read array mode and to asynchronous page mode read configuration. a read array command written to a partition that is performing an erase or program operation will present invalid data until the operation completes; it will then display array data when read. if an erase- or program-suspend command suspends the wsm, a subsequent read array command will place the addressed partition in read array mode. the read array command functions independently of v pp . 4.3 read identifier command the read identifier mode outputs the manufacturer/device identifier, block lock status, protection register codes, and configuration register. the identifier plane occupies the 4-mbit partition address range supplied by the read identifier command (90h) address. reads from addresses in table 7 retrieve id information. issuing a read identifier command to a partition that is programming or erasing places that partition ? s outputs in read id mode while the partition continues to program or erase in the background. notes: 1. the address is constructed from a base address plus an offset. for example, to read the block lock status for block number 38 in a bpd, set the address to the bba (0f8000h) plus the offset (02h), i.e. 0f8002h. then examine bit 0 of the data to determine if the block is locked. 2. see section 4.12.4, ? block lock status ? on page 29 for valid lock status. table 7. device identification codes item address (1) data description base offset manufacturer id partition 00h 0089h device id partition 01h 8862h 32-mbit tpd 8863h 32-mbit bpd 8864h 64-mbit tpd 8865h 64-mbit bpd 8866h 128-mbit tpd 8867h 128-mbit bpd block lock status (2) block 02h dq[0] = 0 block is unlocked dq[0] = 1 block is locked block lock-down status (2) block 02h dq[1] = 0 block is not locked-down dq[1] = 1 block is locked down configuration register partition 05h register data protection register lock status partition 80h lock data protection register partition 81h - 88h register data multiple reads required to read the entire 128-bit protection register.
1.8 volt intel ? wireless flash memory (w18) preliminary 15 4.4 read query command the query plane comes to the foreground and occupies a 4-mbit address range at the partition supplied by the read query command address. the mode outputs cfi data when partition addresses are read. appendix b, ? common flash interface ? on page 68 shows query mode information and addresses. issuing a read query command to a partition that is programming or erasing places that partition ? s outputs in read query mode while the partition continues to program or erase in the background. 4.5 read status register command the device ? s status register displays program and erase operation status. a partition ? s status can be read after writing the read status register command to the partition ? s address range. the status register can also be read following a program, erase, or lock block command sequence. subsequent single reads from that partition will return its status until another valid command is written. the read status mode supports single synchronous and single asynchronous reads only; it doesn ? t support page mode or burst reads. the first oe# or ce# falling edge latches and updates status register data. the operation doesn ? t affect other partitions ? modes. dq[7:0] outputs status register data while dq[15:8] outputs 00h. see table 8, ? status register definitions ? on page 16 . the status register occupies the 4-mbit partition to which the read status, program, or erase command was issued. status register bit sr.7 is the dws (device wsm status) bit and provides program and erase status of the device. the pws (partition write/erase status) bit tells whether the addressed partition or some other partition is actively programming or erasing. status register bits sr.6-1 present information about the wsm ? s program, erase, suspend, v pp , and block-lock status. table 9, ? status register dws and pws description ? on page 16 presents descriptions of dws (sr.7) and pws (sr.0) combinations.
1.8 volt intel ? wireless flash memory (w18) 16 preliminary table 8. status register definitions dws ess es ps vpps pss dps pws 7 6 5 4 3 2 1 0 bit name state description 7 dws device wsm status 0 = device wsm is busy 1 = device wsm is ready sr.7 indicates erase or program completion in the device. sr.1 ? 6 are invalid while sr.7 = 0. see table 9 for valid sr.7 and sr.0 combinations. 6 ess erase suspend status 0 = erase in progress/completed 1 = erase suspended after issuing an erase suspend command, the wsm halts and sets sr.7 and sr.6. sr.6 remains set until the device receives an erase resume command. 5 es erase status 0 = erase successful 1 = erase error sr.5 is set if an attempted erase failed. a command sequence error is indicated when sr.4, sr.5 and sr.7 are set. 4 ps program status 0 = program successful 1 = program error sr.4 is set if the wsm failed to program a word. 3 vpps vpp status 0 = v pp ok 1 = v pp low detect, operation aborted the wsm indicates the v pp level after program or erase completes. sr.3 does not provide continuous v pp feedback and isn ? t guaranteed when v pp v pp1/2 . 2 pss program suspend status 0 = program in progress/completed 1 = program suspended after receiving a program suspend command, the wsm halts execution and sets sr.7 & sr.2. they remain set until a resume command is received. 1 dps device protect status 0 = unlocked 1 = aborted erase/program attempt on locked block if an erase or program operation is attempted to a locked block (if wp# = v il ), the wsm sets sr.1 and aborts the operation. 0 pws partition write status 0 = depending on sr.7 ? s state, the addressed partition is busy or no other partition is busy. 1 = another partition is busy addressed partition or another partition is erasing or programming. in efp mode, sr.0 indicates that a data- stream word has finished programming or verifying depending on the particular efp phase. see table 9 for valid sr.7 and sr.0 combinations. table 9. status register dws and pws description dws (sr.7) pws (sr.0) description 0 0 the addressed partition is performing a program/erase operation. efp: device is finished programming or verifying data or is ready for data. 0 1 a partition other than the one currently addressed is performing a program/erase operation. efp: the device is either programming or verifying data. 1 0 no program/erase operation is in progress in any partition. erase and program suspend bits (sr.6 and sr.2) indicate whether other partitions are suspended. efp: the device has exited efp mode. 1 1 won ? t occur in standard program or erase modes. efp: this combination will not occur.
1.8 volt intel ? wireless flash memory (w18) preliminary 17 4.6 clear status register command the clear status register command clears the status register and leaves all partition output states unchanged. the command functions independently of the applied v pp voltage. the wsm can set all status register bits and clear bits 0, 2, 6, and 7. because bits 1, 3, 4 and 5 indicate various error conditions, they can only be cleared by the clear status register command. by allowing system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence), may be performed before reading the status register to determine error occurrence. the status register should be cleared before beginning another command or sequence. device reset (rst# = v il ) also clears the status register. 4.7 word program command writing a word program command to the device initiates internally timed sequences that program the requested word. programming can occur in only one partition at a time. other partitions must be in one of the read modes or in erase suspend mode. note that only one partition at a time can be in erase suspend mode. the wsm executes a sequence of internally timed events to program desired bits at the addressed location and verify that the bits are sufficiently programmed. programming the memory changes specifically addressed bits to ? 0. ? ? 1 ? bits do not change the memory cell contents. the status register can be examined for program progress and errors by reading any address within the partition that ? s programming. issuing a read status register command to other partitions brings the status register to the foreground in those partitions, allowing program progress to be monitored or detected at other device addresses. status register bit sr.7 indicates device program status while the program sequence executes. ce# or oe# toggle (during polling) updates the status register. valid commands that can be issued to the programming partition during programming are read status register, program suspend, read identifier, read query, and read array (which returns unknown data). when programming completes, sr.4=1 indicates program failure. if sr.3 is set, the wsm couldn ? t execute the word program command because v pp was outside acceptable limits. if sr.1 is set, the program operation targeted a locked block and was aborted. after examining the status register, it should be cleared by the clear status register command before issuing a new command. the partition remains in status register mode until another command is written to that partition. any command can follow once program completes.
1.8 volt intel ? wireless flash memory (w18) 18 preliminary 4.8 block erase command the two-cycle block erase command sequence, consisting of erase setup (20h) and erase confirm (d0h), initiates one block erase at the addressed block. only one partition can be in an erase mode at a time; other partitions must be in a read mode. the erase confirm command internally latches the address of the block to be erased. erase forces all bits within the block to ? 1 ? . sr.7 is cleared while the erase executes. figure 2. word program flowchart suspend program loop start write 40h, word address write data word address read status register sr.7 = full program status check (if desired) program complete full program status check procedure suspend program read status register program successful sr.3 = sr.1 = 0 0 sr.4 = 0 1 1 1 1 0 no yes v pp range error device protect error program error word program procedure sr.3 must be cleared before the wsm will allow further program attempts only the clear staus register command clears sr.1, 3, 4. if an error is detected, clear the status register before attempting a program retry or other error recovery. standby standby bus operation command check sr.3 1 = v pp error check sr.4 1 = data program error comments repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. comments bus operation command data = 40h addr = location to program (wa) write program setup data = data to program (wd) addr = location to program (wa) write data read srd toggle ce# or oe# to update srd read check sr.7 1 = wsm ready 0 = wsm busy standby standby check sr.1 1 = attempted program to locked block program aborted
1.8 volt intel ? wireless flash memory (w18) preliminary 19 after writing the erase confirm command, the selected partition is placed in read status register mode and reads performed to that partition will return current status data. the cpu can detect block erase completion by analyzing sr.7 of that partition. sr.5=1 indicates an erase failure, sr.3=1 indicates an invalid v pp supply voltage, and sr.1=1 indicates an erase operation was attempted on a locked block. if an error bit was flagged, the status register can be cleared by issuing the clear status register command before attempting the next operation. the partition will remain in read status register mode until another command is written to its cui. any cui instruction can follow once erasing completes. the cui can be set to read array mode to prevent inadvertent status register reads. figure 3. block erase flowchart sr. 1 and 3 must be cleared before the wsm will allow further erase attempts. only the clear status register command clears sr.1, 3, 4, 5. if an error is detected, clear the status register before attempting an erase retry or other error recovery. start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block erase or after a sequence of block erasures. no suspend erase 1 0 0 0 1 1 1 1 0 yes suspend erase loop 0 write 20h block address write d0h and block address read status register sr.7 = full erase status check (if desired) block erase complete read status register block erase successful sr.1 = erase of locked block aborted block erase procedure bus operation command comments write block erase setup data = 20h addr = block to be erased (ba) write erase confirm data = d0h addr = block to be erased (ba) read read srd toggle ce# or oe# to update srd standby check sr.7 1 = wsm ready 0 = wsm busy bus operation command comments sr.3 = v pp range error sr.4,5 = command sequence error sr.5 = block erase error standby check sr.3 1 = v pp error standby check sr.4,5 both 1 = command sequence error standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block erase aborted
1.8 volt intel ? wireless flash memory (w18) 20 preliminary 4.9 program suspend, program resume erase suspend, erase resume commands the program suspend and erase suspend commands halt an in - progress program or erase operation. the command can be issued at any device address. the partition corresponding to the command ? s address remains in its previous state. the suspend command allows data to be accessed from memory locations other than the one being programmed or the block being erased. a program operation can be suspended to perform reads only. an erase operation can be suspended to perform either a program or a read operation within any block, except the block that is erase suspended. a program command nested within a suspended erase can subsequently be suspended to read yet another location. once a program/erase process starts, the suspend command requests that the wsm suspend the program/erase sequence at predetermined points in the algorithm. the partition that is actually suspended continues to output status register data after the suspend command is written. an operation is suspended when status bits sr.7 and sr.6 and/or sr.2 display ? 1 ? . t whrh1 /t ehrh1 specifies suspend latency. to read data from blocks within the partition (other than an erase-suspended block), a read array command can be written. during erase suspend, a program command can be issued to a block other than the erase-suspended block. block erase cannot resume until program operations initiated during erase suspend complete. read array, read status register, read identifier (id), read query, and program resume are valid commands during program or erase suspend. additionally, clear status register, program, program suspend, erase resume, lock block, unlock block, and lock-down block are valid commands during erase suspend. to read data from a block in a partition that is not programming/erasing, the operation does not need to be suspended. if the other partition is already in read array, id, or query mode, issuing a valid address will return corresponding data. if the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. during a suspend, ce# = v ih places the device in standby state, which reduces active current. v pp must remain at its program level and wp# must remain unchanged while in suspend mode. a resume command instructs the wsm to continue programming or erasing and clears status register bits sr.2 (or sr.6) and sr.7. the resume command can be written to any partition. when read at the partition that is programming or erasing, the device outputs data corresponding to the partition ? s last mode. if status register error bits are set, the status register can be cleared before issuing the next instruction. rst# must remain at v ih . see figure 4, ? program suspend/resume flowchart ? on page 21 and figure 5, ? erase suspend/resume flowchart ? on page 22 . if a suspended partition was placed in read array, read status register, read identifier (id), or read query mode during the suspend, the device remains in that mode and outputs data corresponding to that mode after the program or erase operation is resumed. after resuming a suspend operation, issue the read command appropriate to the read operation. to read status after resuming a suspended operation, issue a read status register command (70h) to return the suspended partition to status mode. a minimum t whwh time should elapse between an erase command and a subsequent erase suspend command to ensure that the device achieves sufficient cumulative erase time. occasional erase-to-suspend interrupts do not cause problems, but erase-to-suspend commands issued too frequently may produce undetermined results.
1.8 volt intel ? wireless flash memory (w18) preliminary 21 figure 4. program suspend/resume flowchart read status register sr.7 = sr.2 = write ffh susp partition read array data program completed done reading write ffh pgm ? d partition write d0h any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure write program resume data = d0h addr = any device address bus operation command comments write program suspend data = b0h addr = any address within programming partition standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = program suspended 0 = program completed write read array data = ffh addr = any device address (except word being programmed) read read array data from block other than the one being programmed read read srd toggle ce# or oe# to update srd addr = any address in same partition start write b0h any address write 70h same partition write read status data = 70h addr = any address in same partition if the suspended partition was placed in read array mode: write read status return partition to status mode: data = 70h addr = address within same partition write 70h same partition
1.8 volt intel ? wireless flash memory (w18) 22 preliminary figure 5. erase suspend/resume flowchart erase completed write ffh erased partition read array data 0 0 no read 1 program program loop read array data 1 yes start write b0h any address read status register sr.7 = sr.6 = write d0h any address erase resumed read or program? done? write write standby standby write erase suspend read array or program erase resume data = b0h addr = any address data = ffh or 40h addr = any device address (except block being erased) check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = any address bus operation command comments read read srd toggle ce# or oe# to update srd addr = any address in same partition read or write read array or program data from/to block other than the one being erased erase suspend / resume procedure write 70h same partition write read status data = 70h addr = any address in same partition write 70h same partition if the suspended partition was placed in read array mode or a program loop: write read status return partition to status mode: data = 70h addr = address within same partition
1.8 volt intel ? wireless flash memory (w18) preliminary 23 4.10 enhanced factory program command (efp) efp substantially improves device programming performance via a number of enhancements to the conventional 12-volt word program algorithm. efp ? s more efficient wsm algorithm eliminates the traditional overhead delays of conventional word program mode in both the host programming system and the flash device. changes to the conventional word programming flowchart and internal wsm routine were developed because of today ? s beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was struck. after a single command sequence, host programmer bus cycles write data words followed by status checks to determine when the next data word is ready to be accepted. this modification essentially cuts write bus cycles in half. following each internal program pulse, the wsm increments the device ? s address to the next physical location. now, programming equipment can sequentially stream program data throughout an entire block without having to setup and present each new address. in combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. additionally, efp speeds up programming by performing internal code verification. with this, prom programmers can rely on the device to verify that it ? s been programmed properly. from the device side, efp streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. efp consists of four phases: setup, program, verify and exit. refer to figure 6, ? enhanced factory program flowchart ? on page 26 for a detailed graphical representation on how to implement efp. 4.10.1 efp requirements and considerations efp requirements: ambient temperature: t a = 25 c 5 c v cc within specified operating range v pp within specified v pp2 range target block unlocked efp considerations: block cycling below 10 erase cycles (1) rww not supported (2) efp programs one block at a time efp cannot be suspended 1. recommended for optimum performance. some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. 2. code or data cannot be read from another partition during efp. see figure 6, ? enhanced factory program flowchart ? on page 26 for a detailed flowchart on how to implement an efp operation.
1.8 volt intel ? wireless flash memory (w18) 24 preliminary 4.10.2 setup phase after receiving the efp setup (30h) and efp confirm (d0h) command sequence, sr.7 transitions from a ? 1 ? to a ? 0 ? indicating that the wsm is busy with efp algorithm startup. a delay before checking sr.7 is required to allow the wsm time to perform all of its setups and checks (v pp level and block lock status). if an error is detected, status register bits sr.4, sr.3 and/or sr.1 are set and efp operation terminates. note: after the efp setup and confirm command sequence, reads from the device automatically output status register data. do not issue the read status register command; it will be interpreted as data to program at wa0. 4.10.3 program phase after setup completion, the host programming system must check sr.0 to determine "data-stream ready" status (sr.0=0). each subsequent write after this is a program-data write to the flash array. each cell within the memory word to be programmed to ? 0 ? will receive one wsm pulse; additional pulses, if required, occur in the verify phase. sr.0=1 indicates that the wsm is busy applying the program pulse. the host programmer must poll the device's status register for the "program done" state after each data-stream write. sr.0=0 indicates that the appropriate cell(s) within the accessed memory location have received their single wsm program pulse, and that the device is now ready for the next word. although the host may check full status for errors at any time, it is only necessary on a block basis, after efp exit. addresses must remain within the target block. supplying an address outside the target block immediately terminates the program phase; the wsm then enters the efp verify phase. the address can either hold constant or it can increment. the device compares the incoming address to that stored from the setup phase (wa 0 ); if they match, the wsm programs the new data word at the next sequential memory location. if they differ, the wsm jumps to the new address location. the program phase concludes when the host programming system writes to a different block address, data supplied must be ffffh. upon program phase completion, the device enters the efp verify phase. 4.10.4 verify phase a high percentage of the flash bits program on the first wsm pulse. however, for those cells that do not completely program on their first attempt, efp internal verification identifies them and applies additional pulses as required. the verify phase is identical in flow to that of the program phase, except that instead of programming incoming data, the wsm compares the verify-stream data to that which was previously programmed into the block. if the data compares correctly, the host programmer proceeds to the next word. if not, the host waits while the wsm applies an additional pulse(s). the host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. it then reissues each data word in the same order it did during the program phase. like programming, the host may write each subsequent data word to wa 0 or it may increment up through the block addresses.
1.8 volt intel ? wireless flash memory (w18) preliminary 25 the verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be ffffh. upon verify phase completion, the device enters the efp exit phase. 4.10.5 exit phase sr.7=1 indicates that the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. after efp exit, any valid cui command can be issued.
1.8 volt intel ? wireless flash memory (w18) 26 preliminary figure 6. enhanced factory program flowchart efp setup efp program efp verify efp exit 1. wa 0 = first word address to be programmed within the target block. the bba (block base address) must remain constant throughout the program phase data stream; wa can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. writing to a bba not equal to that of the block currently being written to terminates the efp program phase, and instructs the device to enter the efp verify phase. 2. for proper verification to occur , the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. writing to a bba not equal to wa terminates the efp verify phase, and instructs the device to exit efp . 3. bits that did not fully program with the single wsm pulse of the efp program phase receive additional program-pulse attempts during the efp verify phase. the device will report any program failure by setting sr.4=1; this check can be performed during the full status check after efp has been exited for that block, and will indicate any error within the entire data stream. comments bus state repeat for subsequent operations. after efp exit, a full status check can determine if any program error occurred. see the full status check procedure in the word program flowchart. write standby read write write (note 2) read standby write read standby efp setup program done? exit program phase last data? exit verify phase efp exited? write efp confirm read standby efp setup done? read standby verify stream ready? write unlock block write (note 1) standby last data? standby (note 3) verify done? sr.0=1=n write data address = wa 0 last data? write ffffh address bba program done? read status register sr.0 = 0 = y y sr.0=1=n n write data address = wa 0 verify done? last data? read status register write ffffh address bba y verify stream ready? read status register sr.7=0=n full status check procedure operation complete read status register efp exited? sr.7 = 1 = y sr.0=1=n start write 30h address = wa 0 v pp = 12v unlock block write d0h address = wa 0 efp setup done? read status register sr.7 = 1 = n exit n efp program efp verify efp exit efp setup enhanced factory programming procedure comments bus state data = 30h address = wa 0 data = d0h address = wa 0 status register check sr.7 0 = efp ready 1 = efp not ready v pp = 12v unlock block check sr.0 0 = program done 1 = program not done status register data = ffffh address not within same bba data = data to program address = wa 0 device automatically increments address. comments bus state data = word to verify address = wa 0 status register device automatically increments address. data = ffffh address not within same bba status register check sr.0 0 = ready for verify 1 = not ready for verify check sr.0 0 = verify done 1 = verify not done status register check sr.7 0 = exit not finished 1 = exit completed check v pp & lock errors (sr.3, sr.1) data stream ready? read status register sr.0 = 0 = y sr.7=0=y sr.0=1=n standby read data stream ready? check sr.0 0 = ready for data 1 = not ready for data status register sr.0 = 0 = y sr.0 = 0 = y efp setup time standby efp setup time standby error condition check if sr.7 = 1: check sr.3, sr.1 sr.3 = 1 = v pp error sr.1 = 1 = locked block
1.8 volt intel ? wireless flash memory (w18) preliminary 27 4.11 security modes the 1.8 volt intel ? wireless flash memory offers both hardware and software security features to protect the flash data. the software security feature is used by executing the lock block command. the hardware security feature is used by executing the lock-down block command and by asserting the wp# signal. refer to figure 7, ? block locking state diagram ? on page 28 for a state diagram of the flash security features. also see figure 8, ? locking operations flowchart ? on page 30 . 4.12 block locking commands individual instant block locking protects code and data by allowing any block to be locked or unlocked with no latency. this locking scheme offers two levels of protection. the first allows software-only control of block locking (useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed (protects infrequently changed code blocks). the following sections discuss the locking system operation. the term ? state [xyz] ? specifies locking states; e.g., ? state [001], ? where x = wp# value, y = block lock status register bit dq 1 , and z = block lock status register bit dq 0 . figure 7, ? block locking state diagram defines possible locking states. the following summarizes the locking functionality. all blocks power-up in a locked state. unlock commands can unlock these blocks. the lock-down command locks a block and prevents it from being unlocked when wp# = v il . ? wp# = v ih overrides lock-down so commands can unlock or lock blocks. ? when wp# returns to v il , previously locked-down blocks return to lock-down. ? the lock-down state is cleared only when the device is reset or powered-down. each block ? s locking status can be set to locked, unlocked, and lock-down, as described in the following sections. figure 7, ? block locking state diagram ? on page 28 shows the state table for the locking functions. see also figure 8, ? locking operations flowchart ? on page 30 .
1.8 volt intel ? wireless flash memory (w18) 28 preliminary notes: 1. the notation [x,y,z] denotes the locking state of a block, the current locking state of a block is defined by the state of wp# and the two bits of the block-lock status dq[1:0]. 4.12.1 lock block all blocks default to locked (states [001] or [101]) after initial power-up or reset. locked blocks are fully protected from alteration. attempted program or erase operations to a locked block will return an error in sr.1. unlocked blocks can be locked by using the lock block command sequence. similarly, a locked block ? s status can be changed to unlocked or lock-down using the appropriate software commands. 4.12.2 unlock block unlocked blocks (states [000], [100], [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered-down. an unlocked block ? s status can be changed to the locked or locked-down state using the appropriate software commands. a locked block can be unlocked by writing the unlock block command sequence if the block is not locked-down. 4.12.3 lock-down block locked-down blocks (state [011]) offer the user an addition level of write protection beyond that of a regular locked block. a block that is locked-down cannot have it ? s state changed by software if wp# is asserted. a locked or unlocked block can be locked-down by writing the lock-down block figure 7. block locking state diagram wp# write protection is enabled in these states while the lock-down status bit is set. (dq[1]=1) locked [x01] unlocked [x00] locked [111] unlocked [110] locked- down [011] unlock cmd wp#=x lock cmd wp#=x u n l o c k c m d w p # = 1 w p # = 0 l o c k c m d w p # = 1 l o ck-down c m d wp#=x wp#=0 w p # = 1 l o c k - d o w n c m d w p # = x device in reset or powered-down wp# dq[1] dq[0] block status x00unlocked x 0 1 locked 0 1 1 locked down 110unlocked 1 1 1 locked (all other combinations are invalid)
1.8 volt intel ? wireless flash memory (w18) preliminary 29 command sequence. if a block was set to locked-down, then later changed to unlocked, asserting wp# will force that block back to the locked-down. when wp# is deasserted, locked-down blocks are changed to the locked state and can then be unlocked by unlock block command. locked- down blocks revert to the locked state at device reset or power-down. 4.12.4 block lock status every block ? s lock status can be read in read identifier mode. to enter this mode, write 90h to the device. subsequent reads at block address + 02h will output that block ? s lock status. for example, to read the block lock status of block 10, the address sent to the device should be 50002h (for a top- parameter device). the lowest two data bits, dq[1] and dq[0], represent the lock status. dq[0] indicates the block lock status. it is set by the lock block command and cleared by the block unlock command. it is also set when entering lock-down state. dq[1] indicates lock-down status and is set by the lock-down command. the lock-down status bit cannot be cleared by software, only by device reset or power-down. see table 10 . 4.12.5 locking operations during erase suspend block lock configurations can be performed during an erase suspend operation by using the standard locking command sequences to unlock, lock, or lock-down a block. this feature is useful when another block requires immediate updating. to change block locking during an erase operation, first write the erase suspend command. after checking sr.6 to determine the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. after completing lock, unlock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits will change immediately. but, when resumed, the erase operation will complete. locking operations cannot occur during program suspend. appendix a, ? write state machine states ? on page 65 shows valid commands during erase suspend. 4.12.6 status register error checking using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. since locking changes require two-cycle command sequences, e.g., 60h followed by 01h to lock a block, following the configuration setup command (60h) with an invalid command produces a command sequence error (sr.4=1 and sr.5=1). if a lock block command error occurs during erase suspend, the device sets sr.4 and sr.5 to ? 1 ? even after the erase is resumed. when erase is table 10. write protection truth table vpp wp# rst# write protection x x v il device inaccessible v il x v ih word program and block erase prohibited x v il v ih all lock-down blocks locked x v ih v ih all lock-down blocks can be unlocked
1.8 volt intel ? wireless flash memory (w18) 30 preliminary complete, possible errors during the erase cannot be detected via the status register because of the previous locking command error. a similar situation occurs if a program operation error is nested within an erase suspend. 4.12.7 wp# lock-down control wp# allows block lock-down to be overridden. table 10, ? write protection truth table ? on page 29 defines the write protection methods. wp# controls the lock-down function. wp# = v il protects locked-down blocks [011] from program, erase, and lock status changes. when wp# = v ih , the block ? s lock-down state reverts to locked [111]. a software command can then individually unlock a block [110] for erase or program operations. these blocks can then be re-locked [111] while wp# remains high. when wp# returns low, previously locked-down blocks are forced back to the lock-down state [011] regardless of changes made while wp# was high. device reset or power-down resets all blocks to the locked state [101] or [001]. 4.13 protection register the 1.8 volt intel ? wireless flash memory includes a 128-bit protection register. this protection register is used to increase system security and/or for identification purposes. the protection register value can match the flash component to the system ? s cpu or asic to prevent device substitution. figure 8. locking operations flowchart no optional start write 60h block address write 90h bba + 02h read block lock status locking change? lock change complete write 01,d0,2fh block address write ffh partition address yes write write write (optional) read (optional) standby (optional) write lock setup lock, unlock, or lockdown confirm read id plane block lock status read array data = 60h addr = block to lock/unlock/lock-down (ba) data = 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr = block to lock/unlock/lock-down (ba) data = 90h addr = bba + 02h block lock status data addr = bba + 02h confirm locking change on dq[1:0]. (see block locking state transitions table for valid combinations.) data = ffh addr = any address in same partition bus operation command comments locking operations procedure
1.8 volt intel ? wireless flash memory (w18) preliminary 31 the lower 64 bits within the protection register are programmed by intel with a unique number in each flash device. the upper 64 otp bits within the protection register are left for the customer to program. once programmed, the customer segment can be locked to prevent further programming. note that the individual bits of the user segment of the protection register are otp, not the register in total. the user may program each otp bit individually, one at a time, if desired. once the protection register is locked, however, the entire user segment is locked and no more user bits may be programmed. the protection register shares some of the same internal flash resources as the parameter partition. therefore, rww is only allowed between the protection register and main partitions. table 11 describes the operations allowed in the protection register, parameter partition, and main partition during rww and rwe. 4.14 read protection register writing the read identifier command allows the protection register data to be read 16 bits at a time from addresses shown in table 7, ? device identification codes ? on page 14 . the protection register is read via the read identifier command and can be read in any partition.writing the read array command returns the device to read array mode. 4.15 program protection register the protection program command should be issued only at the bottom partition followed by the data to be programed at the specified location. it programs the upper 64 bits of the protection register 16 bits at a time. table 7, ? device identification codes ? on page 14 shows allowable addresses. see also figure 9, ? protection register programming flowchart ? on page 32 . issuing a protection program command outside the register ? s address space results in a status register error (sr.4=1). table 11. simultaneous operations allowed with the protection register protection register parameter partition array data main partitions description read see description write/erase while programming or erasing in a main partition, the protection register may be read from any other partition. reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. see description read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers from parameter partition addresses is not allowed. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers in a partition that is different from the one being programed/erased, and also different from the parameter partition, is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to the parameter partition is not allowed. this is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. reads in other main partitions are supported.
1.8 volt intel ? wireless flash memory (w18) 32 preliminary 4.15.1 lock protection register pr-lk.0 is programmed to ? 0 ? by intel to protect the unique device number. pr-lk.1 can be programmed by the user to lock the user portion (upper 64 bits) of the protection register (see figure 10, ? protection register locking ). this bit is set using the protection program command to program ? fffdh ? into pr-lk. after pr-lk register bits are programmed (locked), the protection register ? s stored values can ? t be changed. protection program commands written to a locked section result in a status register error (sr.4=1, sr.5=1). . figure 9. protection register programming flowchart full status check procedure protection program operations addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. sr.3 must be cleared before the wsm will allow further program attempts. only the clear staus register command clears sr.1, 3, 4. if an error is detected, clear the status register before attempting a program retry or other error recovery. yes no 1,1 0,1 1,1 protection register programming procedure start write c0h addr=prot addr write protect. register address / data read status register sr.7 = 1? full status check (if desired) program complete read srd program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = v pp range error programming error locked-register program aborted standby standby bus operation command sr.1 sr.3 sr.4 011v pp error 0 0 1 protection register program error comments write write standby protection program setup protection program data = c0h addr = protection address data = data to program addr = protection address check sr.7 1 = wsm ready 0 = wsm busy bus operation command comments read read srd toggle ce# or oe# to update srd standby 1 0 1 register locked; operation aborted
1.8 volt intel ? wireless flash memory (w18) preliminary 33 figure 10. protection register locking lock register 0 4 words (64 bits) user programmed group 1 4 words (64 bits) intel factory programmed group 0 84h 88h 85h 81h 80h prot_reg.wmf
1.8 volt intel ? wireless flash memory (w18) 34 preliminary 4.16 set configuration register the set configuration register command sets the burst order, frequency configuration, burst length, and other parameters. a two-bus cycle command sequence initiates this operation. the configuration register data is placed on the lower 16 bits of the address bus (a[15:0]) during both bus cycles. the set configuration register command is written along with the configuration data (on the address bus). this is followed by a second write that confirms the operation and again presents the configuration register data on the address bus. the configuration register data is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). this command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. the configuration register ? s contents can be examined by writing the read identifier command and then reading location 05h. table 12. configuration register definitions read mode res ? d first access latency count wait polarity data output config wait config burst seq clock config res ? d res ? d burst wrap burst length rm r lc2 lc1 lc0 wt doc wc bs cc r r bw bl2 bl1 bl0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name description notes (1) 15 rm read mode 0 = synchronous burst reads enabled 1 = asynchronous reads enabled (default) 2 14 r reserved 13-11 lc2-0 first access latency count 000 = code 0 (reserved) 001 = code 1 (reserved) 010 = code 2 011 = code 3 100 = code 4 101 = code 5 110 = code 6 (reserved) 111 = code 7 (reserved) (default) 10 wt wait signal polarity 0 = wait signal is active low 1 = wait signal is active high (default) 3 9 doc data output configuration 0 = hold data for one clock 1 = hold data for two clock (default) 8 wc wait configuration 0 = wait asserted during delay 1 = wait asserted one data cycle before delay (default) 7 bs burst sequence 0 = intel burst order 1 = linear burst order (default) 6 cc clock configuration 0 = burst starts and data output on falling clock edge 1 = burst starts and data output on rising clock edge (default) 5 r reserved 4 r reserved 3 bw burst wrap 0 = wrap bursts within burst length set by cr.2 ? 0 1 = don ? t wrap accesses within burst length set by cr.2 ? 0.(default) 2-0 bl2-0 burst length 001 = 4-word burst 010 = 8-word burst 011 = reserved 111 = continuous burst (default) 4
1.8 volt intel ? wireless flash memory (w18) preliminary 35 notes: 1. undocumented combinations of bits are reserved by intel for future implementations. 2. synchronous and page read mode configurations affect reads from main blocks and parameter blocks. status register and configuration reads support single read cycles. cr.15=1 disables configuration set by cr.14-1. 3. data is not ready when wait is active. 4. set the synchronous burst length. in asynchronous page mode, the burst length equals four words. 4.16.1 read mode (cr.15) all partitions support two high-performance read configurations: synchronous burst mode and asynchronous page mode (default). cr.15 sets the read configuration to one of these modes. status register, query, and identifier modes support only asynchronous and single-synchronous read operations. 4.16.2 first access latency count (cr.13-11) the first access latency count (cr.13-11) configuration tells the device how many clocks must elapse from adv#-inactive (v ih ) before the first data word should be driven onto its data pins. the input clock frequency determines this value. see table 12, ? configuration register definitions ? on page 34 for latency values. figure 13, ? first access latency configuration ? on page 37 shows data output latency from adv#-active for different latencies. use these equations to calculate first access latency count: (1) {1/ frequency} = clk period (2) n (clk period) t avqv (ns) + t add-delay (ns) + t data (ns) (3) n-2 = first access latency count (lc) * n: # of clock periods (rounded up to the next integer) *must use lc = n - 1 when the starting address is not aligned to a four-word boundary and cr.3=1 (no wrap). ) table 13. first latency count (lc) lc setting mode wrap aligned to 4-word boundary wait asserted on 16-word boundary crossing n-1 4 or 8 disabled no yes, occurs on the every occurrence n-2 4 or 8 disabled yes no n-2 4 or 8 enabled no no n-2 4 or 8 enabled yes no n-1 continuous x x yes, occurs once
1.8 volt intel ? wireless flash memory (w18) 36 preliminary note: 1. the 16-word boundary is the end of the device sense word-line. parameters defined by cpu : t add-delay = clock to ce#, adv#, or address valid whichever occurs last. t data = data set up to clock. parameters defined by flash : t avqv = address to output delay. example : cpu clock speed = 52 mhz t add-delay = 6 ns (typical speed from cpu) (max) t data = 4 ns (typical speed from cpu) (min) t avqv = 70 ns (from ac characteristic - read only operations table) from eq. (1): 1/52 (mhz) = 19.2 ns from eq. (2) n(19.2 ns) 70 ns + 6 ns + 4 ns n(19.2 ns) 80 ns n 80/19.2 = 4.17 = 5 (integer) from eq. (3) n - 2 = 5 - 2 = 3 first access latency count setting to the cr is code 3. ( figure 12, ? data output with lc setting at code 3 ? on page 37 displays example data) the formula t avqv (ns) + t add-delay (ns) + t data (ns) is also known as initial access time. figure 12 shows the data output available and valid after four clocks from adv# going low in the first clock period with the lc setting at 3. figure 11. word boundary 0123456789abcdef 16 word boundary word 0 - 3 word 4 - 7 word 8 - b word c - f 4 word boundary
1.8 volt intel ? wireless flash memory (w18) preliminary 37 4.16.3 wait signal polarity (cr.10) the wait signal polarity is set by cr.10 (wt). if the wt bit is cleared (cr.10=0), then wait is configured to be active low. this means that a ? 0 ? on the wait signal indicates that data is not ready and the data bus contains invalid data. conversely, if cr.10 is set (cr.10=1), then wait is active high. in either case, if wait is deasserted, then data is ready and valid. figure 12. data output with lc setting at code 3 figure 13. first access latency configuration address [a] dq[15:0] [q] clk [c] ce# [e] adv# [v] r103 valid output valid output high z t add t data 2nd 1st 3rd 4th 5th valid address code 3 code 1 (reserved code 6 (reserved) code 5 code 4 code 3 code 2 code 0 (reserved) code 7 (reserved) valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] dq[15:0] [q] clk [c] dq[15:0] [q] dq[15:0] [q] dq[15:0] [q] dq[15:0] [q] dq[15:0] [q] dq[15:0] [q] dq[15:0] [q]
1.8 volt intel ? wireless flash memory (w18) 38 preliminary wait is high-z until the device is active (ce# = v il ). in synchronous read array mode, when the device is active (ce# = v il ) and data is valid, cr.10 determines if wait goes to v oh or v ol . the wait signal is only ? deasserted ? once data is valid on the bus. invalid data drives the wait signal to the asserted state. wait is asserted during asynchronous page mode reads. 4.16.4 wait signal function the wait signal indicates data valid when the device is operating in synchronous burst mode (cr.15=0), and when addressing a partition that is currently in read array mode. the wait signal is only ? deasserted ? when data is valid on the bus. when the device is operating in synchronous non-read array mode, such as read status, read id, or read query, wait is set to an ? asserted ? state as determined by cr.10. figure 25, ? wa i t s i g n a l i n synchronous non-read array operation waveform ? on page 58 displays wait signal in synchronous non-read array operation waveform. when the device is operating in asynchronous page mode or asynchronous single word read mode, wait is set to an ? asserted ? state as determined by cr.10. see figure 26, ? wait signal in asynchronous page-mode read operation waveform ? on page 59 and figure 27, ? wa it sig na l in asynchronous single-word read operation waveform ? on page 60 . from a system perspective, the wait signal will be in the asserted state (based on cr.10) when the device is operating in synchronous non-read array mode (such as read id, read query, or read status), or if the device is operating in asynchronous mode (cr.15=1). in these cases, the system software should ignore (mask) the wait signal, as it does not convey any useful information about the validity of what is appearing on the data bus. systems may tie several components ? wait signals together. 4.16.5 data output configuration (cr.9) the data output configuration bit (cr.9) determines whether a data word remains valid on the data bus for one or two clock cycles. the processor ? s minimum data set-up time and the flash memory ? s clock-to-data output delay determine whether one or two clocks are needed. if the data output configuration is set at one-clock data hold, this corresponds to a one-clock data cycle; if the data output configuration is set at two-clock data hold, this corresponds to a two- clock data cycle. this configuration bit ? s setting depends on the system and cpu characteristics. refer to figure 14, ? data output configuration with wait signal delay ? on page 39 for clarification. a method for determining what this configuration should be set at is shown below. to set the device at one clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) as an example, a clock frequency of 52 mhz will be used. the clock period is 19.2 ns. this data is applied to the formula above for the subsequent reads assuming the data output hold time is one clock: 14 ns + 4 ns 19.2 ns
1.8 volt intel ? wireless flash memory (w18) preliminary 39 this equation is satisfied and data output will be available and valid at every clock period. if t data is long, hold for two cycles. now assume the clock frequency is 66 mhz. this corresponds to a 15 ns period. the initial access time is calculated to be 80 ns (latency count = code 4). this condition satisfies t avqv (ns) + t add-delay (ns) + t data (ns) = 70 ns + 6 ns + 4 ns = 80 ns, as shown above in the first access latency count equations. however, the data hold time of one clock violates the one-clock data hold condition: t chqv (ns) + t data (ns) one clk period 14 ns + 4 ns = 18 ns is not less than one clock period of 15 ns. to satisfy the formula above, the data output hold time must be set at 2 clocks to correctly allow for data output setup time. this formula is also satisfied if the cpu has t data (ns) 1 ns, which yields: 14 ns + 1 ns 15 ns in page-mode reads, the initial access time can be determined by the formula: t add-delay (ns) + t data (ns) + t avqv (ns) and subsequent reads in page mode are defined by: t apa (ns) + t data (ns) (minimum time) 4.16.6 wait delay configuration (cr.8) the wait configuration bit (cr.8) controls wait signal delay behavior for all synchronous read array modes. its setting depends on the system and cpu characteristics. the wait can be asserted either during or one data cycle before a valid output. figure 14. data output configuration with wait signal delay dq[15:0] [q] clk [c] valid output valid output valid output dq[15:0] [q] valid output valid output 1 clk data hold wait (cr.8 = 1) wait (cr.8 = 0) t chqv t chqv wait (cr.8 = 0) wait (cr.8 = 1) 2 clk data hold t chtl/h note 1 note 1 note 1 note 1 note1: wait shown active high (cr.10 = 1)
1.8 volt intel ? wireless flash memory (w18) 40 preliminary in synchronous linear read array (no-wrap mode cr.3=1) of 4-, 8-, or continuous-word burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16- word boundary). if the burst start address is four-word boundary aligned, the delay will not occur. if the start address is misaligned to a four-word boundary, the delay occurs once per burst-mode read sequence. the wait signal informs the system of this delay. 4.16.7 burst sequence configuration (cr.7) the burst sequence specifies the synchronous burst mode data order ( table 14, ? sequence and burst length ? on page 41 ). set this bit for linear or intel burst order. continuous burst mode supports only linear burst order. when operating in a linear burst mode, either 4-word or 8-word burst length with the burst wrap bit (cr.3) set, or in continuous burst mode, the device may incur an output delay when the burst sequence crosses the first 16-word boundary. (see figure 11, ? word boundary ? on page 36 for word boundary description.) this is dependent on the starting address. if the starting address is aligned to a four-word boundary, the delay will not occur. if the starting address is the end of a four-word boundary, the output delay will be one clock cycle less than the first access latency count; this is the worst-case delay. the delay will take place only once and will not happen if the burst sequence does not cross a 16-word boundary. the wait pin informs the system of this delay. see figure 22, ? single synchronous read operation waveform ? on page 55 through figure 24, ? wait functionality for eowl (end of word line) condition waveform ? on page 57 for timing diagrams of wait functionality.
1.8 volt intel ? wireless flash memory (w18) preliminary 41 4.16.8 clock configuration (cr.6) clock-edge facilitates easy memory interface to a wide range of burst cpus. clock configuration sets the device to start a burst cycle, output data, and assert wait on the clock ? s rising or falling edge. 4.16.9 burst wrap (cr.5) the burst wrap bit determines whether 4-word or 8-word burst accesses wrap within the burst- length boundary or whether they cross word-length boundaries to perform linear accesses. no- wrap mode (cr.3=1) enables wait to hold off the system processor, as it does in the continuous burst mode, until valid data is available. in the no-wrap mode (cr.3=0), the device operates similar to continuous linear burst mode but consumes less power during 4 or 8-word bursts. for example, if cr.3=0 (wrap mode) and cr.2 ? 0 = 1h (4-word burst), possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. table 14. sequence and burst length start addr. (dec) wrap cr.3= 0 no wrap cr.3= 1 burst addressing sequence (dec) 4-word burst length cr.2 ? 0 = 001 8-word burst length cr.2 ? 0 = 010 continuous burst cr.2 ? 0 = 111 linear intel linear intel linear 0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-... 1 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-... 2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-... 3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-... 4 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3- 4-5-6-7-8-9-10... 5 0 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11... 6 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-... 7 0 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... ... ... ... ... ... ... ... ... 14 0 14-15-16-17-18-19-20-... 15 0 15-16-17-18-19-20-21-... ... ... ... ... ... ... ... ... 0 1 0-1-2-3 na 0-1-2-3-4-5-6-7 na 0-1-2-3-4-5-6-... 1 1 1-2-3-4 na 1-2-3-4-5-6-7-8 na 1-2-3-4-5-6-7-... 2 1 2-3-4-5 na 2-3-4-5-6-7-8-9 na 2-3-4-5-6-7-8-... 3 1 3-4-5-6 na 3-4-5-6-7-8-9-10 na 3-4-5-6-7-8-9-... 4 1 4-5-6-7-8-9-10-11 na 4-5-6-7-8-9-10... 5 1 5-6-7-8-9-10-11-12 na 5-6-7-8-9-10-11... 6 1 6-7-8-9-10-11-12-13 na 6-7-8-9-10-11-12-... 7 1 7-8-9-10-11-12-13-14 na 7-8-9-10-11-12-13... ... ... ... ... ... ... ... ... 14 1 14-15-16-17-18-19-20-... 15 1 15-16-17-18-19-20-21-...
1.8 volt intel ? wireless flash memory (w18) 42 preliminary if cr.3=1 (no-wrap mode) and cr.2 ? 0 = 1h (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. cr.3=1 not only enables limited non-aligned sequential bursts, but also reduces power by minimizing the number of internal read operations. setting cr.2-0 bits for continuous linear burst mode (7h) also achieves the above 4-word burst sequences. however, significantly more power may be consumed. the 1-2-3-4 sequence, for example, will consume power during the initial access, again during the internal pipeline lookup as the processor reads word 2, and possibly again, depending on system timing, near the end of the sequence as the device pipelines the next 4-word sequence. cr.3=1 while in 4-word burst mode (no wrap mode) reduces this excess power consumption. 4.16.10 burst length (cr.2-0) the burst length is the number of words the device outputs in a synchronous read access. 4-, 8-, and continuous burst lengths are supported. in 4- or 8-word burst configuration, the burst wrap bit (cr.3) determines if burst accesses wrap within word-length boundaries or whether they cross word-length boundaries to perform a linear access. once an address is given, the device will output data until it reaches the end of its burstable address space. continuous burst access are linear only and do not wrap within word-length boundaries. (see table 14, ? sequence and burst length ? on page 41 ).
1.8 volt intel ? wireless flash memory (w18) preliminary 43 5.0 program and erase voltages the 1.8 volt intel ? wireless flash memory provides in-system program and erase at v pp1 . for factory programming, it also includes a low-cost, backward-compatible 12 v programming feature. the efp feature can also be used to greatly improve factory program performance. 5.1 factory program mode the standard factory programming mode uses the same commands and algorithm as the word program mode (40h/10h). when v pp is at v pp1 , program and erase currents are drawn through vcc. note that if vpp is driven by a logic signal, v pp1 must remain above the v pp1 min value to perform in-system flash modifications. when vpp is connected to a 12 v power supply, the device draws program and erase current directly from vpp. this eliminates the need for an external switching transistor to control the v pp voltage. figure 15, ? example vpp power supply configuration shows examples of flash power supply usage in various configurations. the 12 v v pp mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during program and erase operations as specified in section 7.2, ? extended temperature operation ? on page 47 . vpp may be connected to 12 v for a total of t pph hours maximum. stressing the device beyond these limits may cause permanent damage. 5.2 programming voltage protection (v pp ) in addition to the flexible block locking, holding the v pp programming voltage low can provide absolute hardware write protection of all flash-device blocks. if v pp is below v pplk , program or erase operations will result in an error displayed in sr.3. note: 1. if the v cc supply can sink adequate current, an appropriately valued resistor can be used. figure 15. example vpp power supply configuration ? 12 v fast programming ? absolute write protection with v pp v pplk system supply (note 1) v cc v pp 12 v supply v cc v pp ? low voltage and 12 v fast programming system supply 12 v supply ? low-voltage programming ? absolute write protection via logic signal system supply v cc v pp prot# (logic signal) ? low-voltage programming system supply v cc v pp 10k ? vppsuply.wmf (note 2) 1 2 3 4
1.8 volt intel ? wireless flash memory (w18) 44 preliminary 6.0 power consumption 1.8 volt intel ? flash memory devices have a layered approach to power savings that can significantly reduce overall system power consumption. the aps feature reduces power consumption when the device is selected but idle. if ce# is de-asserted, the memory enters its standby mode, where current consumption is even lower. asserting rst# provides current savings similar to standby mode. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 6.1 active power with ce# at v il and rst# at v ih , the device is in the active mode. refer to the section 7.4, ? dc characteristics ? on page 48 , for i cc values. 6.2 automatic power savings aps mode provides low - power operation during read mode. after data is read from the memory array and the address lines are quiescent, aps circuitry places the device in a mode where typical current is comparable to i ccs . the flash stays in this static state with outputs valid, oe# low, until a new location is read. 6.3 standby power with ce# at v ih and the device in read mode, the flash memory is in standby mode, which disables most device circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the oe# signal state. if ce# transitions to v ih during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is complete. 6.4 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. it does not matter whether v pp or v cc powers-up first. power supply sequencing is not required. 6.4.1 system reset and rst# the use of rst# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rst# to the system cpu reset# signal to allow proper cpu/flash initialization at system reset. system designers must guard against spurious writes when vcc voltages are above v lko . since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rst# is brought to v ih , regardless of its control input states. by
1.8 volt intel ? wireless flash memory (w18) preliminary 45 holding the device in reset (rst# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 6.4.2 vcc, vpp, and rst# transitions the cui latches commands issued by system software and is not altered by vpp or ce# transitions or wsm actions. read array mode is its power-up default state after exit from reset mode or after vcc transitions above v lko (lockout voltage). after completing program or block erase operations (even after vpp transitions below v pplk ), the read array command must reset the cui to read array mode if flash memory array access is desired. 6.4.3 power supply decoupling when the device is accessed, many internal conditions change. circuits are enabled to charge pumps and switch voltages. this internal activity produces transient noise. to minimize the effect of this transient noise, device decoupling capacitors are required. transient current magnitudes depend on the device outputs ? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each power (vcc, vccq, vpp) , and ground (vss, vssq) signal. high-frequency, inherently low-inductance capacitors should be as close as possible to package signals.
1.8 volt intel ? wireless flash memory (w18) 46 preliminary 7.0 electrical specifications 7.1 absolute maximum ratings notes: 1. all specified voltages are with respect to vss. minimum dc voltage is ? 0.5 v on input/output pins and ? 0.2 v on vcc and vpp pins. during transitions, this level may undershoot to ? 2.0 v for periods <20 ns which, during transitions, may overshoot to v cc +2.0 v for periods < 20 ns. 2. maximum dc voltage on vpp may overshoot to +14.0 v for periods < 20 ns. 3. v pp program voltage is normally v pp1 . v pp can be 12v 0.6 v for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 4. output shorted for no more than one second. no more than one output shorted at a time. warning: stressing the device beyond the ? absolute maximum ratings ? may cause permanent damage. these are stress ratings only. operation beyond the ? operating conditions ? is not recommended and extended exposure beyond the ? operating conditions ? may affect device reliability. parameter note maximum rating temperature under bias ? 40 c to +85 c storage temperature ? 65 c to +125 c voltage on any pin (except vcc, vccq, vpp) 1 ? 0.5 v to +2.45 v vpp voltage 1,2,3 ? 0.2 v to +14 v vcc and vccq voltage 1 ? 0.2 v to +2.45 v output short circuit current 4 100 ma notice: this datasheet contains preliminary information on new products in production. specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design .
1.8 volt intel ? wireless flash memory (w18) preliminary 47 7.2 extended temperature operation notes: 1. see dc characteristics tables for voltage-range specific specifications. 2. vpp is normally v pp1 . vpp can be connected to 11.4 v?12.6 v for 1000 cycles on main blocks for extended temperatures and 2500 cycles at extended temperature on parameter blocks. 3. contact your intel field representative for enhanced v cc /v ccq operations down to 1.65 v. 7.3 capacitance t a = +25 c, f = 1 mhz note: sampled, not 100% tested. symbol parameter (1) note min nom max unit t a operating temperature ? 40 25 85 c v cc v cc supply voltage 3 1.7 1.80 1.95 v v ccq i/o supply voltage 3 1.7 1.80 2.24 v v pp1 v pp voltage supply (logic level) 2 0.90 1.80 1.95 v v pp2 factory programming v pp 2 11.4 12.0 12.6 v t pph maximum v pp hours v pp = 12 v 2 80 hours block erase cycles main and parameter blocks v pp v cc 2 100,000 cycles main blocks v pp = 12 v 2 1000 cycles parameter blocks v pp = 12 v 2 2500 cycles sym parameter (1) 32/64 mbit 128 mbit unit condition typ max typ max c in input capacitance 6 8 8 9 pf v in = 0.0 v c out output capacitance 8 12 8 12 pf v out = 0.0 v c ce ce# input capacitance 10 12 10 12 pf v in = 0.0 v
1.8 volt intel ? wireless flash memory (w18) 48 preliminary 7.4 dc characteristics sym parameter (1) note 32/64 mbit 128 mbit unit test condition typ max ty p max i li input load current 1 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current dq[15:0] 1 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current 5 18 5 25 a v cc = v cc max v ccq = v ccq max ce# = v cc rst# =v cc or gnd i ccr average v cc read current synchronous clk = 40 mhz 2, 3 6 13 6 13 ma burst length = 4 v cc = v cc max ce# = v il oe# = v ih inputs = v ih or v il 8 14 8 14 ma burst length = 8 11 20 11 20 ma burst length = continuous synchronous clk = 52 mhz 2, 3 7 16 7 16 ma burst length = 4 10 18 10 18 ma burst length = 8 13 25 13 25 ma burst length = continuous i ccw v cc program current 4, 5 18 40 18 40 ma v pp = v pp1, program in progress 8 15 8 15 ma v pp = v pp2, program in progress i cce v cc block erase current 4, 6 18 40 18 40 ma v pp = v pp1, block erase in progress 8 15 8 15 ma v pp = v pp2, block erase in progress i ccws v cc program suspend current 4, 7 5 18 5 25 a ce# = v cc, program suspended i cces v cc erase suspend current 4, 7 5 18 5 25 a ce# = v cc, erase suspended i pps (i ppws, i ppes ) v pp standby current v pp program suspend current v pp erase suspend current 4 0.2 5 0.2 5 a v pp < v cc i ppr v pp read current 2 15 2 15 a v pp v cc i ppw v pp program current 4 0.05 0.10 0.05 0.10 ma v pp = v pp1, program in progress 8 22 8 22 v pp = v pp2, program in progress i ppe v pp erase current 4 0.05 0.10 0.05 0.10 ma v pp = v pp1, erase in progress 8 22 8 22 v pp = v pp2, erase in progress
1.8 volt intel ? wireless flash memory (w18) preliminary 49 dc characteristics, continued notes: 1. all currents are rms unless noted. typical values at typical v cc , t a = +25 c. 2. aps reduces i ccr to approximately standby levels in static operation. 3. cr.3 determines whether 4- or 8-word burst accesses wrap within the burst-length boundary or whether they cross word-length boundaries to perform linear accesses. in the no-wrap mode (cr.3=1), the device operates similar to continuous linear burst mode but consumes less power. 4. sampled, not 100% tested. 5. v cc read + program current is the summation of v cc read and v cc program currents. 6. v cc read + erase current is the summation of v cc read and v cc block erase currents. 7. i cces is specified with device deselected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . 8. v il can undershoot to ? 0.4 v and v ih can overshoot to v ccq +0.4 v for durations of 20 ns or less. 9. erase and program operations are inhibited when v pp v pplk and not guaranteed outside valid v pp1 and v pp2 ranges. sym parameter note min typ max unit test condition v il input low voltage 8 0 0.4 v v ih input high voltage 8 v ccq ? 0.4 v ccq v v ol output low voltage 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ? 0.1 v v cc = v cc min v ccq = v ccq min i oh = ? 100 a v pplk v pp lock-out voltage 9 0.4 v v lko v cc lock voltage 1.0 v
1.8 volt intel ? wireless flash memory (w18) 50 preliminary 7.5 ac i/o test conditions note: ac test inputs are driven at v ccq for a logic ?1? and 0.0 v for a logic ?0?. input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v cc = v cc min. 0672_22 note: see table for component values. test configuration component value for worst case speed conditions note: c l includes jig capacitance. figure 16. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input output figure 17. transient equivalent testing load circuit device under test v ccq c l r 2 r 1 out test configuration c l (pf) r 1 ( ? ) r 2 ( ? ) v ccq min standard test 30 16.7k 16.7k figure 18. clock input ac waveform clk [c] v ih v il r203 r202 r201
1.8 volt intel ? wireless flash memory (w18) preliminary 51 7.6 ac read characteristics # sym parameter (1,2) notes 32/64 mbit 128 mbit unit ? 70 ? 85 -90 min max min max min max asynchronous specifications r1 t avav read cycle time 70 85 90 ns r2 t avqv address to output delay 70 85 90 ns r3 t elqv ce# low to output delay 70 85 90 ns r4 t glqv oe# low to output delay 4 30 30 30 ns r5 t phqv rst# high to output delay 150 150 150 ns r6 t elqx ce# low to output in low-z 5 0 0 0 ns r7 t glqx oe# low to output in low-z 4 , 5 0 0 0 ns r8 t ehqz ce# high to output in high-z 5 20 25 25 ns r9 t ghqz oe# high to output in high-z 4 , 5 20 25 25 ns r10 t oh ce# (oe#) high to output in low-z 4 , 5 0 0 0 ns latching specifications r101 t avvh address setup to adv# high 10 10 10 ns r102 t elvh ce# low to adv# high 10 10 10 ns r103 t vlqv adv# low to output delay 70 85 90 ns r104 t vlvh adv# pulse width low 10 10 10 ns r105 t vhvl adv# pulse width high 10 10 10 ns r106 t vhax address hold from adv# high 3 9 9 9 ns r108 t apa page address access time 20 25 30 ns clock specifications r200 f clk clk frequency 52 40 40 mhz r201 t clk clk period 19 25 25 ns r202 t ch/l clk high or low time 5 5 5 ns r203 t chcl clk fall or rise time 3 3 3 ns
1.8 volt intel ? wireless flash memory (w18) 52 preliminary x notes: 1. see figure 16, ? ac input/output reference waveform ? on page 50 for timing measurements and maximum allowable input slew rate. 2. ac specifications assume the data bus voltage is less than or equal to v ccq when a read operation is initiated. 3. address hold in synchronous burst-mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 4. oe# may be delayed by up to t elqv ? t glqv after the falling edge of ce# without impact to t elqv . 5. sampled, not 100% tested. 6. applies only to subsequent synchronous reads. synchronous specifications r301 t avch address valid setup to clk 9 9 9 ns r302 t vlch adv# low setup to clk 10 10 10 ns r303 t elch ce# low setup to clk 9 9 9 ns r304 t chqv clk to output valid 14 18 18 ns r305 t chqx output hold from clk 3.5 3.5 3.5 ns r306 t chax address hold from clk 3 10 10 10 ns r307 t chtv clk to wait valid 14 18 18 ns r308 t eltv ce# low to wait valid 6 14 18 18 ns r309 t ehtz ce# high to wait high-z 5 , 6 20 25 25 ns r310 t ehel ce# pulse width high 6 15 20 20 ns # sym parameter (1,2) notes 32/64 mbit 128 mbit unit ? 70 ? 85 -90 min max min max min max figure 19. asynchronous read operation waveform v ih v il valid address v ih v il v ih v il v ih v il high z v oh v ol valid output v ih v il r1 r2 r3 r4 r5 r6 r7 r10 address [a] f-ce# [e] f-oe# [g] f-we# [w] data [d/q] f-rst# [p] r8 r9
1.8 volt intel ? wireless flash memory (w18) preliminary 53 figure 20. latched asynchronous read operation waveform v oh v ol high z valid output v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il data [q] we# [w] oe# [g] ce# [e] a[max:2] [a] adv# [v] rst# [p] r102 r104 r1 r2 r3 r4 r5 r6 r7 r10 r103 r101 r105 r106 a[1:0] [a] v ih v il valid address valid address valid address r8 r9
1.8 volt intel ? wireless flash memory (w18) 54 preliminary figure 21. page-mode read operation waveform r105 v ih v il v ih v il v ih v il v ih v il v oh v ol high z valid output valid output valid output valid output v ih v il v ih v il valid address v ih v il valid address valid address valid address valid address r102 r104 adv# [v] ce# [e] oe# [g] we# [w] data [q] rst# [p] a[max:2] [a] a[1:0] [a] r1 r2 r101 r106 r103 r3 r4 r7 r6 r108 r10 r5 r9 r8
1.8 volt intel ? wireless flash memory (w18) preliminary 55 notes: 1. section 4.16.2, ? first access latency count (cr.13-11) ? on page 35 describes how to insert clock cycles during the initial access. 2. wait (shown active low) can be configured to assert either during or one data cycle before valid data. figure 22. single synchronous read operation waveform note 1 v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il v oh v ol v oh v ol high z valid output v ih v il r101 r102 r302 r301 r306 r2 r106 r105 r103 r3 r4 r7 r8 r9 r10 r5 r305 high z r304 clk [c] rst# [p] address [a] adv# [v] oe# [g] we# [w] wait [t] data [q] ce# [e] r303 r104 high z r308 r309 note 2
1.8 volt intel ? wireless flash memory (w18) 56 preliminary notes: 1. section 4.16.2, ? first access latency count (cr.13-11) ? on page 35 describes how to insert clock cycles during the initial access. 2. wait (shown active low) can be configured to assert either during or one data cycle before valid data. figure 23. synchronous four-word burst read operation waveform v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il valid address v ih v il note 1 v oh v ol valid output valid output valid output valid output high z r105 r102 r301 r302 r306 r101 r2 r106 r103 r3 r4 r7 r304 r5 r305 r8 r9 01 rst# [p] wait [t] we# [w] oe# [g] ce# [e] adv# [v] address [a] clk [c] data [q] note 2 r104 r303 r10 r307 high z r308 r309 r310 high z high z
1.8 volt intel ? wireless flash memory (w18) preliminary 57 notes: 1. section 4.16.2, ? first access latency count (cr.13-11) ? on page 35 describes how to insert clock cycles during the initial access. 2. wait (shown active low) can be configured to assert either during or one data cycle before valid data. figure 24. wait functionality for eowl (end of word line) condition waveform v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il valid address v ih v il note 1 v oh v ol valid output valid output valid output valid output high z r105 r102 r301 r302 r306 r101 r2 r106 r103 r3 r4 r7 r304 r5 r305 01 rst# [p] wait [t] we# [w] oe# [g] ce# [e] adv# [v] address [a] clk [c] data [d/q] note 2 r104 r303 r307 high z r308 high z
1.8 volt intel ? wireless flash memory (w18) 58 preliminary notes: 1. section 4.16.2, ? first access latency count (cr.13-11) ? on page 35 describes how to insert clock cycles during the initial access. 2. wait shown active low. figure 25. wait signal in synchronous non-read array operation waveform note 1 v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il v oh v ol v oh v ol high z valid output v ih v il r101 r102 r302 r301 r306 r2 r106 r105 r103 r3 r4 r7 r8 r9 r10 r5 r305 high z r304 clk [c] rst# [p] address [a] adv# [v] oe# [g] we# [w] wait [t] data [q] ce# [e] r303 r104 high z r308 r309 note 2
1.8 volt intel ? wireless flash memory (w18) preliminary 59 notes: 1. wait shown active low. figure 26. wait signal in asynchronous page-mode read operation waveform r105 v ih v il v ih v il v ih v il v ih v il v oh v ol high z valid output valid output valid output valid output v ih v il v ih v il valid address v ih v il valid address valid address valid address valid address r102 r104 adv# [v] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] a[max:2] [a] a[1:0] [a] r1 r2 r101 r106 r103 r3 r4 r7 r6 r108 r10 r5 r9 r8 v oh v ol high z wait [t] high z note 1
1.8 volt intel ? wireless flash memory (w18) 60 preliminary notes: 1. wait shown active low. figure 27. wait signal in asynchronous single-word read operation waveform v ih v il valid address v ih v il v ih v il v ih v il high z v oh v ol valid output v ih v il r1 r2 r3 r4 r5 r7 r10 address [a] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] r8 r9 v oh v ol high z wait [t] high z note 1
1.8 volt intel ? wireless flash memory (w18) preliminary 61 7.7 ac write characteristics notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever is first) to ce# or we# low (whichever is last). hence, t whwl = t ehel = t whel = t ehwl . 6. t whqv is t avqv + 50 ns. system designers should take this into account and may insert a software no-op instruction to delay the first read after issuing a command. 7. for command other than resume commands. 8. v pp should be held at v pp1 or v pp2 until block erase or program success is determined. 9. applicable during asynchronous reads following a write. 10.during synchronous reads, either t whcv or t whvh must be met, whichever occurs first. # sym parameter (1,2) notes 32 mbit / 64 mbit 128 mbit unit ? 70 ? 85 -90 min max min max min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) low 3 150 150 150 ns w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) low 0 0 0 ns w3 t wlwh (t eleh ) we# (ce#) write pulse width low 4 45 60 60 ns w4 t dvwh (t dveh ) data setup to we# (ce#) high 45 60 60 ns w5 t avwh (t aveh ) address setup to we# (ce#) high 45 60 60 ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 0 0 ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 0 0 0 ns w8 t whax (t ehax ) address hold from we# (ce#) high 0 0 0 ns w9 t whwl (t ehel ) we# (ce#) pulse width high 5 , 6 , 7 25 25 25 ns w10 t vpwh (t vpeh ) vpp setup to we# (ce#) high 3 200 200 200 ns w11 t qvvl vpp hold from valid srd 3 , 8 0 0 0 ns w12 t qvbl wp# hold from valid srd 3 , 8 0 0 0 ns w13 t bhwh (t bheh ) wp# setup to we# (ce#) high 3 200 200 200 ns w14 t whgl (t ehgl ) write recovery before read 0 0 0 ns w16 t whqv we# high to valid data 6 t avqv + 40 t avqv + 50 t avqv + 50 ns w18 t whav we# high to address valid 9 0 0 0 ns w19 t whcv we# high to clk valid 10 25 25 25 ns w20 t whvh we# high to adv# high 10 25 25 25 ns
1.8 volt intel ? wireless flash memory (w18) 62 preliminary notes: 1. v cc power-up and standby. 2. write program or erase setup command. 3. write valid address and data (for program) or erase confirm command. 4. automated program/erase delay. 5. read status register data (srd) to determine program/erase operation completion. 6. oe# and ce# must be asserted and we# deasserted for read operations. figure 28. write operations waveform note 1 note 2 note 3 note 4 note 5 address [a] v ih v il valid address valid address ce# (we#) [e(w)] v ih v il note 6 oe# [g] v ih v il we# (ce#) [w(e)] v ih v il rst# [p] v ih v il w6 w7 w8 w11 w12 r105 vpp [v] v pph v pplk v il wp# [b] v ih v il data [q] v ih v il data in valid srd adv# [v] v ih v il w16 w1 w2 w3 w4 w9 w10 w13 w14 r101 r106 data in valid address note 6 r104 w5 w18 w19 w20 clk [c] v ih v il
1.8 volt intel ? wireless flash memory (w18) preliminary 63 7.8 erase and program times unless noted otherwise, all above parameters are measured at t a = +25 c and nominal voltages, and they are sampled, not 100% tested. notes: 1. excludes external system-level overhead. 2. exact results may vary based on system overhead. 7.9 reset specifications notes: 1. these specifications are valid for all product versions (packages and speeds). 2. the device may reset if t plph < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to vcc. 4. sampled, but not 100% tested. 5. if rst# is tied to vcc, the device is not ready until t vccph after time when v cc v cc min. 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v cc min. operation symbol parameter description notes v pp1 v pp2 unit typ max typ max erasing and suspending erase time w500 t ers/pb 4-kw parameter block 1,2 0.3 2.5 0.25 2.5 s w501 t ers/mb 32-kw main block 1,2 0.7 4 0.4 4 s suspend latency w600 t susp/p program suspend 1 5 10 5 10 s w601 t susp/e erase suspend 1 5 20 5 20 s conventional word programming program time w200 t prog/w single word 1 12 150 8 130 s w201 t prog/pb 4-kw parameter block 1,2 0.05 .23 0.03 0.07 s w202 t prog/mb 32-kw main block 1,2 0.4 1.8 0.24 0.6 s enhanced factory programming program w400 t efp/w single word 3.5 16 s w401 t efp/pb 4-kw parameter block 1,2 15 ms w402 t efp/mb 32-kw main block 1,2 120 ms operation latency w403 t efp/setup efp setup 5 s w404 t efp/tran program to verify transition 2.7 5.6 s w405 t efp/verify verify 1.7 130 s # symbol parameter (1) notes min max unit p1 t plph rst# low pulse width 2, 3, 4 100 ns p2 t plrh rst# low to device reset during block erase 3, 4, 5 20 s rst# low to device reset during program 3, 4, 5 10 s p3 t vccph vcc power valid to rst# high 1,3,4,5,6 60 s
1.8 volt intel ? wireless flash memory (w18) 64 preliminary figure 29. reset operations waveforms ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v vcc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
1.8 volt intel ? wireless flash memory (w18) preliminary 65 appendix a write state machine states this table shows the command state transitions based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last output state (array, id/cfi or status) until a new command changes it. the next wsm state does not depend on the partition ? s output state. table a1. write state machine - next state table next state after command input read array (3) program setup (4,5) erase setup (4,5) efp setup (4) block erase confirm, pgm/erase resume, ulb confirm (9) program/ erase suspend read status register clear status register (6) read identifier/ query current state (ffh) (10h/ 40h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h) ready ready program setup erase setup efp setup ready lock/cr setup ready (lock error) ready ready (lock error) otp setup otp busy busy otp busy program setup program busy busy program busy program suspend program busy suspend program suspend program busy program suspend erase setup ready (error) erase busy ready (error) busy erase busy erase suspend erase busy suspend erase suspend program in erase suspend setup erase suspend erase busy erase suspend program in erase suspend setup program in erase suspend busy busy program in erase suspend busy program in erase suspend program in erase suspend busy suspend program in erase suspend program in erase suspend busy program in erase suspend lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) efp setup ready (error) efp busy ready (error) busy efp busy (7) verify verify busy (7) state output after command input program erase erase setup otp setup program in erase suspend efp setup, efp busy verify busy status lock/cr setup lock/cr setup in erase suspend status otp busy array (3) status output doesn ? t change status output doesn ? t change status ready program busy program suspend erase busy erase suspend program in erase suspend pgm suspend in erase suspend array status output doesn ? t change status output doesn ? t change id/query
1.8 volt intel ? wireless flash memory (w18) 66 preliminary table a1. write state machine -- next state table (continued) next state after command input lock, unlock, lock-dwn, cr setup (5) otp setup (5) lock block confirm (9) lock-dwn block confirm (9) write cr confirm (9) efp exit (blkadr wao) illegal cmds or efp data (2) wsm operation completes current state (60h) (c0h) (01h) (2fh) (03h) (xxxxh) (other codes) ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy n/a busy otp busy ready program setup program busy n/a busy program busy ready suspend program suspend n/a erase setup ready (error) n/a busy erase busy ready suspend lock/cr setup in erase suspend erase suspend n/a program in erase suspend setup program in erase suspend busy n/a busy program in erase suspend busy erase suspend suspend program in erase suspend busy n/a lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) n/a efp setup ready (error) n/a busy efp busy (7) efp verify efp busy (7) n/a verify verify busy (7) ready efp verify (7) ready state output after command input program erase erase setup otp setup program in erase suspend efp setup efp busy verify busy status output doesn ? t change lock/cr setup lock/cr setup in erase suspend status array status output doesn ? t change otp busy status (7) output doesn ? t change array status output doesn ? t change ready program busy program suspend erase busy erase suspend program in erase suspend pgm suspend in erase suspend status output doesn ? t change array status output doesn ? t change
1.8 volt intel ? wireless flash memory (w18) preliminary 67 notes: 1. the output state shows the type of data that appears at the outputs if the partition address is the same as the command address. a partition can be placed in read array, read status or read id/cfi, depending on the command issued. each partition stays in its last output state (array, id/cfi or status) until a new command changes it. the next wsm state does not depend on the partition ? s output state. for example, if partition #1 ? s output state is read array and partition #4 ? s output state is read status, every read from partition #4 (without issuing a new command) outputs the status register. 2. illegal commands are those not defined in the command set. 3. all partitions default to read array mode at power-up. a read array command issued to a busy partition results in undermined data when a partition address is read. 4. both cycles of 2-cycle commands should be issued to the same partition address. if they are issued to different partitions, the second write determines the active partition. both partitions will output status information when read. 5. if the wsm is active, both cycles of a 2-cycle command are ignored. this differs from previous intel devices. 6. the clear status command clears status register error bits except when the wsm is running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, efp modes) or suspended (erase suspend, pgm suspend, pgm suspend in erase suspend). 7. efp writes are allowed only when status register bit sr.0=0. efp is busy if block address = address at efp confirm command. any other commands are treated as data. 8. the "current state" is that of the wsm, not the partition. 9. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state.
1.8 volt intel ? wireless flash memory (w18) 68 preliminary appendix b common flash interface this appendix defines the data structure or ? database ? returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. b.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device ? s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq[7:0]) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ? q ? and ? r, ? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ? q ? in the low byte (dq[7:0]) and 00h in the high byte (dq[15:8]). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ? h ? suffix has been dropped. in addition, since the upper byte of word-wide devices is ? 00h, ? the leading ? 00 ? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. b.2 query structure overview the read query command causes the flash component to display the cfi query structure or ? database. ? the structure subsections and address locations are summarized below.
1.8 volt intel ? wireless flash memory (w18) preliminary 69 notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. bba = block base address beginning location (i.e., 08000h is block 1 ? s beginning location when the block size is 32k-word). 3. offset 15h defines ? p ? which points to the primary intel-specific extended query table. table b1. query structure offset subsection description (1) 00h manufacturer code 01h device code bba + 02h (2) block status register block-specific information 04h to 0fh reserved reserved for vendor-specific information 10h cfi query identification string command set id and vendor data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash device layout p (3) primary intel-specific extended query table addition vendor-defined information specific to the primary vendor algorithm
1.8 volt intel ? wireless flash memory (w18) 70 preliminary b.3 cfi query identification string the identification string provides verification that the component supports the cfi specification. it also indicates the specification version and supported vendor-specified command set(s). table b2. cfi identification address offset description data value cfi identification 10h query unique ascii string ? qry ? 51h ? q ? 11h 52h ? r ? 12h 59h ? y ? 13h primary vendor command set and control interface id code. 16-bit id code for vendor-specified algorithms 03h 14h 00h 15h extended query table primary algorithm address. (denotes the starting offset address for the vendor-specific query table.) 39h 16h 00h 17h alternate vendor command set and control interface id code. 0000h means no second vendor-specified algorithm exists 00h 18h 00h 19h secondary algorithm extended query table address. 0000h means none exists. 00h 1ah 00h system interface information 1bh vcc logic supply minimum program/erase voltage dq[7:4] = volts (bcd) dq[3:0] = 100mv (bcd) 17h 1.7 v 1ch vcc logic supply maximum program/erase voltage dq[7:4] = volts (bcd) dq[3:0] = 100mv (bcd) 19h 1.9 v 1dh vcc programming supply minimum program/erase voltage dq[7:4] = volts (bcd) dq[3:0] = 100mv (bcd) b4h 11.4 v 1eh vcc programming supply minimum program/erase voltage dq[7:4] = volts (hex) dq[3:0] = 100mv (bcd) c6h 12.6 v 1fh n such that typical single-word program time-out = 2 n s 04h 16 s 20h n such that typical buffer write time-out = 2 n s 00h 21h n such that typical block erase time-out = 2 n ms 0ah 1 s 22h n such that typical full-chip erase time-out = 2 n ms 00h 23h n such that max single-word program time-out = 2 n s 04h 256 s 24h n such that max buffer write time-out = 2 n s 00h 25h n such that max block erase time-out = 2 n ms 03h 8 s 26h n such that max full-chip erase time-out = 2 n ms 00h
1.8 volt intel ? wireless flash memory (w18) preliminary 71 device geometry definition 27h flash density: 2 n bytes 16h 17h 18h 32mbit 64mbit 128mbit 28h data bus width (low byte): 00h=x8, 01h=x16, 02h=x32, 03h=x64 01h x16 29h data bus width (high byte): not used 00h 0 2ah write buffer size: 2 n bytes 00h 0 2bh 00h 0 2ch number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partition 02h 2 2dh erase block region 1 information bits 0 ? 15 = y, y+1 = number of identical-size erase blocks bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes bpd: 00200007h tpd: 32mb = 0100 003eh, 64mb = 0100 007eh, 128mb = 0100 00feh see description 2eh 2fh 30h 31h erase block region 2 information bits 0 ? 15 = y, y+1 = number of identical-size erase blocks bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes bpd: 32mb = 0100 003eh, 64mb = 0100 007eh, 128mb = 0100 00feh tpd: 0020 0007h see description 32h 33h 34h 35h reserved for future erase block region information 36h 37h 38h primary vendor-specific extended query 39h (1) primary extended query table, unique ascii string: ? pri ? 50h ? p ? 3ah 52h ? r ? 3bh 49h ? i ? 3ch major version number, ascii 31h ? 1 ? 3dh minor version number, ascii 33h ? 3 ? table b2. cfi identification (continued) address offset description data value
1.8 volt intel ? wireless flash memory (w18) 72 preliminary 3eh optional feature and command support: bit feature 0 - full chip erase 1 - erase suspend 2 - program suspend 3 - legacy lock/unlock 4 - queued erase 5 - instant individual block locking 6 - protection bits 7 - pagemode read 8 - synchronous read 9 - simultaneous operations bits 10-31 are reserved. 66h bit 0=no bit 1=yes bit 2=yes bit 3=no bit 4=no bit 5=yes bit 6=yes bit 7=no bit 8=yes bit 9=yes 3fh 03h 40h 00h 41h 00h 42h supported functions after program/erase suspend (besides read array, read status, and read query): bit feature 0 - program after erase suspend 01h bit 0=yes 43h block status register mask ( bits 2-16 are reserved) bit feature 0 - block lock status active 1 - block lock-down status active 03h bit 0=yes bit 1=yes 44h 00h 45h highest v cc supported: bits 0-3 : 100mv (bcd) bits 4-7 : volts (bcd) 18h 1.8 v 46h highest v pp supported: bits 0-3 : 100mv (bcd) bits 4-7 : volts (hex) c0h 12.0 v protection register information 47h number of protection register fields in jedec id space. ? 00h ? indicates that 256 fields are available 01h 1 48h protection field 1: protection description bits 0-7 : lower byte of protection register address bits 8-15 : upper byte of protection register address bits 16-23 : 2 n bytes in factory pre-programmed region bits 24-31 : 2 n bytes in user-programmable region 80h 0080h 49h 00h 5ah 03h 8 bytes 5bh 03h 8 bytes burst read information 5ch page mode read buffer size bits 0-7 : 2 n bytes in read page-mode buffer (00h indicates no page buffer exists for reads) 00h none 5dh number of synchronous read configurations fields that follow. 00h indicates no burst capability 03h 3 fields table b2. cfi identification (continued) address offset description data value
1.8 volt intel ? wireless flash memory (w18) preliminary 73 5eh synchronous read field 1 bits 0-1 : 2 n+1 words per synchronous read bits 2-7 : reserved 01h 4-words 5fh synchronous read field 2 bits 0-1 : 2 n+1 words per synchronous read bits 2-7 : reserved 02h 8-words 60h synchronous read field 3 bits 0-1 : 2 n+1 words per synchronous read bits 2-7 : reserved 07h continuous table b2. cfi identification (continued) address offset description data value table b3. partition and erase block region information feature description bottom-parameter top-parameter adrs 32 mbit 62 mbit 128 mbit adrs 32 mbit 64 mbit 128 mbit number of device hardware partition regions n = number of partition regions containing one or more contiguous erase block regions 51h 02 51h 02 partition region 1 information number of identical partitions within partition region 1 52h 01 52h 07 0f 1f 53h 00 53h 00 number of program or erase operations allowed in partition region 1: bits 0-3 : number of simultaneous program operations bits 4-7 : number of simultaneous erase operations 54h 11 54h 11 number of program or erase operations allowed in other partitions while a partition in this region is programming bits 0-3 : number of simultaneous program operations bits 4-7 : number of simultaneous erase operations 55h 00 55h 00 number of program or erase operations allowed in other partitions while a partition in this region is erasing bits 0-3 : number of simultaneous program operations bits 4-7 : number of simultaneous erase operations 56h 00 56h 00 types of erase block regions in partition region 1 n = number of erase block regions w/ contiguous same-size erase locks. symmetrically blocked partitions have one blocking region. 57h 02 57h 01 partition region 1 erase block type 1 information bits 0-15 : n+1 = number of identical-sized erase blocks bits 16-31 : n 256 = number of bytes in erase block region 58h 07 58h 07 59h 00 59h 00 5ah 20 5ah 00 5bh 00 5bh 01 partition region 1 (erase block type 1) minimum block erase cycles 1000 5ch 64 5ch 64 5dh 00 5dh 00 partition region 1 (erase block type 1): bits per cell, internal ecc bits 0-3 : bits per cell in erase region bit 4 : reserved for ? internal ecc used ? bits 5-7 : reserved 5eh 01 5eh 01
1.8 volt intel ? wireless flash memory (w18) 74 preliminary partition region 1 (erase block type 1): page mode and synchronous mode capabilities (defined in table 10) bit 0 : page-mode host reads permitted bit 1 : synchronous host reads permitted bit 2 : synchronous host writes permitted bits 3-7 : reserved 5fh 02 5fh 02 partition region 1 erase block type 2 information bits 0-15 : n+1 = number of identical-sized erase blocks bits 16-31 : n 256 = number of bytes in erase block region 60h 06 61h 00 62h 00 63h 01 partition region 1 (erase block type 2) minimum block erase cycles 1000 64h 64 65h 00 partition regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3 : bits per cell in erase region bit 4 : reserved for ? internal ecc used ? bits 5-7 : reserved 66h 01 partition region 1 (erase block type 2): page mode and synchronous mode capabilities (defined in table 10) bit 0 : page-mode host reads permitted bit 1 : synchronous host reads permitted bit 2 : synchronous host writes permitted bits 3-7 : reserved 67h 02 partition region 2 information number of identical partitions within partition region 2 68h 07 0f 1f 60h 01 69h 00 61h 00 number of program or erase operations allowed in partition region 2: bits 0-3 : number of simultaneous program operations bits 4-7 : number of simultaneous erase operations 6ah 01 62h 11 number of program or erase operations allowed in other partitions while a partition in this region is programming bits 0-3 : number of simultaneous program operations bits 4-7 : number of simultaneous erase operations 6bh 00 63h 00 number of program or erase operations allowed in other partitions while a partition in this region is erasing bits 0-3 : number of simultaneous program operations bits 4-7 : number of simultaneous erase operations 6ch 00 64h 00 types of erase block regions in partition region 2 n = number of erase block regions w/ contiguous same-size erase locks. symmetrically blocked partitions have one blocking region. 6dh 01 65h 02 partition region 2 erase block type 1 information bits 0-15 : n+1 = number of identical-sized erase blocks bits 16-31 : n 256 = number of bytes in erase block region 6eh 07 66h 06 6fh 00 67h 00 70h 00 68h 00 71h 01 69h 00 partition region 2 (erase block type 1) minimum block erase cycles 1000 72h 64 6ah 01 73h 00 6bh 64 partition region 2 (erase block type 1): bits per cell, internal ecc bits 0-3 : bits per cell in erase region bit 4 : reserved for ? internal ecc used ? bits 5-7 : reserved 74h 01 6ch 01 table b3. partition and erase block region information (continued) feature description bottom-parameter top-parameter adrs 32 mbit 62 mbit 128 mbit adrs 32 mbit 64 mbit 128 mbit
1.8 volt intel ? wireless flash memory (w18) preliminary 75 notes: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. for a 16mb the 1.8 volt intel ? wireless flash memory z1 = 0100h = 256 ? 256 2 = 64k, y1 = 17h = 23d ? y1+1 = 24 ? 24 * 64k = 1 ? mb ? partition 2 ? s offset is 0018 0000h bytes (000c 0000h words). 3. tpd - top parameter device; bpd - bottom parameter device. 4. partition region: symmetrical partitions form a partition region. (there are two partition regions, a. contains all the partitions that are made up of main blocks only. b. contains the partition that is made up of the parameter and the main blocks. partition region 2 (erase block type 1): page mode and synchronous mode capabilities (defined in table 10) bit 0 : page-mode host reads permitted bit 1 : synchronous host reads permitted bit 2 : synchronous host writes permitted bits 3-7 : reserved 75h 02 6dh 02 partition region 2 erase block type 2 information bits 0-15 : n+1 = number of identical-sized erase blocks bits 16-31 : n 256 = number of bytes in erase block region 6eh 07 6fh 00 70h 02 71h 00 partition region 2 (erase block type 2) minimum block erase cycles 1000 72h 64 73h 00 partition region 2 (erase block type 2): bits per cell, internal ecc bits 0-3 : bits per cell in erase region bit 4 : reserved for ? internal ecc used ? bits 5-7 : reserved 74h 01 partition region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in table 10) bit 0 : page-mode host reads permitted bit 1 : synchronous host reads permitted bit 2 : synchronous host writes permitted bits 3-7 : reserved 75h 02 feature space definitions : reserved 76h 76h reserved 77h 77h table b3. partition and erase block region information (continued) feature description bottom-parameter top-parameter adrs 32 mbit 62 mbit 128 mbit adrs 32 mbit 64 mbit 128 mbit
1.8 volt intel ? wireless flash memory (w18) 76 preliminary appendix c mechanical specifications c.4 the 1.8 volt intel ? wireless flash memory 56 active ball matrix (7x8) 0.75 mm ball pitch package specifications notes: 1. 8 ball direction of the matrix runs parallel to this dimension 2. 7 ball direction of the matrix runs parallel to this dimension 3. 4 outrigger support balls on 128-mbit density only 7 x 8 ball matrix mechanical specifications pkg type density d (width) (1) ( 0.1 mm) e (length) (2) ( 0.1 mm) height (max) vf bga 32 mbit 7.7 mm 9.0 mm 1.0 mm bga* csp 64 mbit 7.7 mm 9.0 mm 1.0 mm vf bga 128 mbit 12.5 mm 12.0 mm 1.0 mm note 3 e d
1.8 volt intel ? wireless flash memory (w18) preliminary 77 appendix d ordering information component ordering information g t 2 8 6 4 0 w 1 8 t 7 0 package designator extended temperature (-25 c to +85 c) gt = .75mm bga* ge = .75mm vfbga 56-ball 7x8 matrix product line designator for all intel ? flash products access speed (ns) (70, 85, 90) product family w18 = 1.8 volt intel ? wireless flash memory v cc = 1.7 v - 1.95 v v ccq = 1.7 v - 2.24 v device density 320 = x16 (32-mbit) 640 = x16 (64-mbit) 128 = x16 (128-mbit) parameter parition t = top parameter device b = bottom parameter device f

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